update version, set hwbld date, use aux on 10m input

3607c771 · Tristan Gingold · 48d4a3c5 · 3607c771 · 3607c771 · 3607c771
Commit 3607c771 authored Jun 12, 2023 by Tristan Gingold
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Showing with 9 additions and 7 deletions

wr2rf_regs_core.vhd hdl/rtl/wr2rf_regs_core.vhd +2 -2

wr2rf_vme.tcl hdl/syn/wr2rf_vme/wr2rf_vme.tcl +1 -1

wr2rf_vme.vhd hdl/top/wr2rf_vme/wr2rf_vme.vhd +6 -4

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--- a/hdl/rtl/wr2rf_regs_core.vhd
+++ b/hdl/rtl/wr2rf_regs_core.vhd
@@ -367,8 +367,8 @@ begin
        init_hwinfo_ident_jtagRemoteDisable_i => '1',
        init_hwinfo_ident_extendedID_i => "0000000",
        init_hwinfo_ident_cardID_i => x"56",
-        init_hwinfo_firmwareVersion_i => x"0000_17_00",
-        init_hwinfo_memMapVersion_i   => x"0000_17_00",
+        init_hwinfo_firmwareVersion_i => x"0000_18_00",
+        init_hwinfo_memMapVersion_i   => x"0000_18_00",
        init_hwinfo_echo_echo_o       => open,

        init_fw_update_i => wb_fw_update_in,

--- a/hdl/syn/wr2rf_vme/wr2rf_vme.tcl
+++ b/hdl/syn/wr2rf_vme/wr2rf_vme.tcl
@@ -32,7 +32,7 @@ read_xdc $projDir/gencores_constraints.xdc
 set start_time [clock seconds]

 #synth_design  -rtl -top ${top} -part ${device} > ${top}_synth.log
-synth_design -top ${top} -part ${device} > ${top}_synth.log
+synth_design -top ${top} -part ${device} -generic g_hwbld_date=${start_time} > ${top}_synth.log
 write_checkpoint -force ${top}_synth

 #source wr2rf_async_regs.tcl

--- a/hdl/top/wr2rf_vme/wr2rf_vme.vhd
+++ b/hdl/top/wr2rf_vme/wr2rf_vme.vhd
@@ -56,6 +56,7 @@ entity wr2rf_vme is
    g_rx_streamer_params  : t_rx_streamer_params := c_rx_streamer_params_RF;
    g_ftw_length          : natural := 48;
    g_offset_length       : natural := 48;
+    g_hwbld_date          : std_logic_vector(31 downto 0) := (others => '0');
    g_ila_debug           : string  := "standard" ); -- standard, rfnco

  port (
@@ -803,8 +804,8 @@ begin
          clk10m_o       => clk_ext_10m_o );

    --  Input for dtmd (to check quality of clocks).
-    --  This is hard-coded to tmg clk 1
-    clk_aux_in <= tmg_clk_i(1);
+    --  This is hard-coded to 10Mhz (to be an input).
+    clk_aux_in <= clk_ext_10m_in;

    ------------------------------------------------------------------------------
    -- Dedicated clock for GTP
@@ -893,7 +894,8 @@ begin
            g_diag_id                        => c_diag_id,
            g_diag_ver                       => c_diag_ver,
            g_diag_ro_size                   => c_diag_ro_size,
-            g_diag_rw_size                   => c_diag_rw_size )
+            g_diag_rw_size                   => c_diag_rw_size,
+            g_hwbld_date                     => g_hwbld_date)
        port map(
            clk_sys_i              => clk_sys_62m5,
            clk_dmtd_i             => clk_dmtd_62m5,
@@ -952,7 +954,7 @@ begin
            tm_link_up_o           => tm_link_up,
            tm_dac_value_o         => open,
            tm_dac_wr_o            => open,
-            tm_clk_aux_lock_en_i   => (others => '0'),
+            tm_clk_aux_lock_en_i   => (others => '1'),
            tm_clk_aux_locked_o    => open,
            tm_time_valid_o        => tm_time_valid,
            tm_tai_o               => tm_tai,