wr2rf_vme.vhd: use internal clock to as bootstrap clock

To reduce noise on the clock

wr2rf_vme.vhd: use internal clock to as bootstrap clock
To reduce noise on the clock
2ca2b19b · Tristan Gingold · faeb4d95 · 2ca2b19b
Commit 2ca2b19b authored Aug 30, 2023 by Tristan Gingold
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Showing with 4 additions and 2 deletions

wr2rf_vme.vhd hdl/top/wr2rf_vme/wr2rf_vme.vhd +4 -2

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--- a/hdl/top/wr2rf_vme/wr2rf_vme.vhd
+++ b/hdl/top/wr2rf_vme/wr2rf_vme.vhd
@@ -337,6 +337,8 @@ architecture rtl of wr2rf_vme is
  signal rst_clk500m_n    : std_logic;
  signal rst_clk500m      : std_logic;

+  signal clk_cfgm         : std_logic;
+
  signal clk_aux_in : std_logic;

  -- Wishbone bus from master
@@ -748,7 +750,7 @@ begin
    inst_BUFGMUX_CTRL : BUFGMUX_CTRL
        port map (
            O  => clk_sys_62m5,        -- 1-bit output: Clock output
-            I0 => clk_dmtd_62m5,       -- 1-bit input: Clock input (S=0)
+            I0 => clk_cfgm,            -- 1-bit input: Clock input (S=0)
            I1 => clk62m5,             -- 1-bit input: Clock input (S=1)
            S  => clk_sys_select );    -- 1-bit input: Clock select

@@ -1917,7 +1919,7 @@ begin
        )
      port map (
        CFGCLK => open,   -- 1-bit output: Configuration main clock output
-        CFGMCLK => open,  -- 1-bit output: Configuration internal oscillator clock output
+        CFGMCLK => clk_cfgm, -- 1b out: Configuration internal oscillator clock output
        EOS => open,      -- 1-bit output: Active high output signal indicating the End Of Startup.
        PREQ => open,     -- 1-bit output: PROGRAM request to fabric output
        CLK => '0',       -- 1-bit input: User start-up clock input