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wr2rf-vme
Commit 286074c7 authored by Tristan Gingold's avatar Tristan Gingold
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Implement beam control simulator (replay a sequence)

parent 021ab304
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Showing with 212 additions and 35 deletions
hdl/rtl/registers/wr2rf_init_regs.cheby
View file @ 286074c7
......@@ -826,6 +826,37 @@ memory-map:
size: 256
x-hdl:
busgroup: True
- block:
name: bmctrl_rfframe
description: Interface to play an ftw sequence
children:
- reg:
name: ctrl
width: 16
access: rw
x-hdl:
write-strobe: True
children:
- field:
name: reset
range: 0
- field:
name: en
range: 1
- field:
name: update
range: 2
x-hdl:
type: wire
- reg:
name: status
width: 16
access: ro
children:
- field:
name: fifo_rdy
description: set as long as fifo is not full
range: 0
- submap:
name: wrpc
interface: wb-16
......
hdl/rtl/registers/wr2rf_vme_regs.vhd
View file @ 286074c7
-- Do not edit. Generated by cheby 1.6.dev0 using these options:
-- -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
-- Generated on Wed May 10 11:16:40 2023 by tgingold
-- Generated on Fri May 12 13:30:55 2023 by tgingold
library ieee;
......@@ -366,6 +366,17 @@ entity wr2rf_vme_regs is
init_xadc_i : in t_wishbone_master_in;
init_xadc_o : out t_wishbone_master_out;
-- REG ctrl
init_bmctrl_rfframe_ctrl_reset_o : out std_logic;
init_bmctrl_rfframe_ctrl_en_o : out std_logic;
init_bmctrl_rfframe_ctrl_update_i : in std_logic;
init_bmctrl_rfframe_ctrl_update_o : out std_logic;
init_bmctrl_rfframe_ctrl_wr_o : out std_logic;
-- REG status
-- set as long as fifo is not full
init_bmctrl_rfframe_status_fifo_rdy_i : in std_logic;
-- WR ptp core (peripheral only)
init_wrpc_i : in t_wishbone_master_in;
init_wrpc_o : out t_wishbone_master_out;
......@@ -732,6 +743,10 @@ architecture syn of wr2rf_vme_regs is
signal init_xadc_tr : std_logic;
signal init_xadc_wack : std_logic;
signal init_xadc_rack : std_logic;
signal init_bmctrl_rfframe_ctrl_reset_reg : std_logic;
signal init_bmctrl_rfframe_ctrl_en_reg : std_logic;
signal init_bmctrl_rfframe_ctrl_wreq : std_logic;
signal init_bmctrl_rfframe_ctrl_wack : std_logic;
signal init_wrpc_re : std_logic;
signal init_wrpc_we : std_logic;
signal init_wrpc_wt : std_logic;
......@@ -2194,6 +2209,29 @@ begin
init_xadc_o.we <= init_xadc_wt;
init_xadc_o.dat(15 downto 0) <= wr_dat_d0;
-- Register init_bmctrl_rfframe_ctrl
init_bmctrl_rfframe_ctrl_reset_o <= init_bmctrl_rfframe_ctrl_reset_reg;
init_bmctrl_rfframe_ctrl_en_o <= init_bmctrl_rfframe_ctrl_en_reg;
init_bmctrl_rfframe_ctrl_update_o <= wr_dat_d0(2);
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
init_bmctrl_rfframe_ctrl_reset_reg <= '0';
init_bmctrl_rfframe_ctrl_en_reg <= '0';
init_bmctrl_rfframe_ctrl_wack <= '0';
else
if init_bmctrl_rfframe_ctrl_wreq = '1' then
init_bmctrl_rfframe_ctrl_reset_reg <= wr_dat_d0(0);
init_bmctrl_rfframe_ctrl_en_reg <= wr_dat_d0(1);
end if;
init_bmctrl_rfframe_ctrl_wack <= init_bmctrl_rfframe_ctrl_wreq;
end if;
end if;
end process;
init_bmctrl_rfframe_ctrl_wr_o <= init_bmctrl_rfframe_ctrl_wack;
-- Register init_bmctrl_rfframe_status
-- Interface init_wrpc
init_wrpc_tr <= init_wrpc_wt or init_wrpc_rt;
process (clk_i) begin
......@@ -2709,9 +2747,9 @@ begin
init_txframe_setpoint7_wack, init_txframe_setpoint8_wack,
init_txframe_noise_wack, init_txframe_control_wack,
init_pll_spi_wack, init_rf_spi_wack, init_rf_wack,
init_framerxtx_wack, init_xadc_wack, init_wrpc_wack,
ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_rf1_rfnco_wack,
ctrl_rf2_rfnco_wack, ctrl_rf1_iqdac_phase_wack,
init_framerxtx_wack, init_xadc_wack, init_bmctrl_rfframe_ctrl_wack,
init_wrpc_wack, ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack,
ctrl_rf1_rfnco_wack, ctrl_rf2_rfnco_wack, ctrl_rf1_iqdac_phase_wack,
ctrl_rf2_iqdac_phase_wack, ctrl_rf1_iqdac_phase_update_wack,
ctrl_rf2_iqdac_phase_update_wack, ctrl_rf1_iqdac_igain_arm_wack,
ctrl_rf1_iqdac_qgain_arm_wack, ctrl_rf2_iqdac_igain_arm_wack,
......@@ -2789,6 +2827,7 @@ begin
init_rf_we <= '0';
init_framerxtx_we <= '0';
init_xadc_we <= '0';
init_bmctrl_rfframe_ctrl_wreq <= '0';
init_wrpc_we <= '0';
ctrl_rf1_vtus_we <= '0';
ctrl_rf2_vtus_we <= '0';
......@@ -3674,6 +3713,18 @@ begin
-- Submap init_xadc
init_xadc_we <= wr_req_d0;
wr_ack_int <= init_xadc_wack;
when "00101" =>
case wr_adr_d0(7 downto 1) is
when "0000000" =>
-- Reg init_bmctrl_rfframe_ctrl
init_bmctrl_rfframe_ctrl_wreq <= wr_req_d0;
wr_ack_int <= init_bmctrl_rfframe_ctrl_wack;
when "0000001" =>
-- Reg init_bmctrl_rfframe_status
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when others =>
wr_ack_int <= wr_req_d0;
end case;
......@@ -3940,20 +3991,24 @@ begin
init_txframe_control_reg, init_pll_spi_i.dat, init_pll_spi_rack,
init_rf_spi_i.dat, init_rf_spi_rack, init_rf_i.dat, init_rf_rack,
init_framerxtx_i.dat, init_framerxtx_rack, init_xadc_i.dat,
init_xadc_rack, init_wrpc_i.dat, init_wrpc_rack, ctrl_rf1_vtus_i.dat,
ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack,
ctrl_rf1_rfnco_i.dat, ctrl_rf1_rfnco_rack, ctrl_rf2_rfnco_i.dat,
ctrl_rf2_rfnco_rack, ctrl_rf1_iqdac_phase_reg,
ctrl_rf2_iqdac_phase_reg, ctrl_rf1_iqdac_igain_arm_reg,
ctrl_rf1_iqdac_qgain_arm_reg, ctrl_rf2_iqdac_igain_arm_reg,
ctrl_rf2_iqdac_qgain_arm_reg, ctrl_rf1_iqdac_igain_i,
ctrl_rf1_iqdac_qgain_i, ctrl_rf2_iqdac_igain_i,
ctrl_rf2_iqdac_qgain_i, ctrl_rf1_iqdac_ctrl_reg,
ctrl_rf2_iqdac_ctrl_reg, ctrl_iqdac_ram_addr_reg,
ctrl_iqdac_ram_data_reg, ctrl_iqdac_ram_write_reg,
ctrl_iqdac_ram_play_reg, ctrl_rf1_dds_ftw_valid_reg,
ctrl_rf1_dds_ftw_reg, ctrl_rf2_dds_ftw_valid_reg,
ctrl_rf2_dds_ftw_reg, ctrl_nco_reset_ctrl_mask_dds_reg,
init_xadc_rack, init_bmctrl_rfframe_ctrl_reset_reg,
init_bmctrl_rfframe_ctrl_en_reg,
init_bmctrl_rfframe_ctrl_update_i,
init_bmctrl_rfframe_status_fifo_rdy_i, init_wrpc_i.dat,
init_wrpc_rack, ctrl_rf1_vtus_i.dat, ctrl_rf1_vtus_rack,
ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack, ctrl_rf1_rfnco_i.dat,
ctrl_rf1_rfnco_rack, ctrl_rf2_rfnco_i.dat, ctrl_rf2_rfnco_rack,
ctrl_rf1_iqdac_phase_reg, ctrl_rf2_iqdac_phase_reg,
ctrl_rf1_iqdac_igain_arm_reg, ctrl_rf1_iqdac_qgain_arm_reg,
ctrl_rf2_iqdac_igain_arm_reg, ctrl_rf2_iqdac_qgain_arm_reg,
ctrl_rf1_iqdac_igain_i, ctrl_rf1_iqdac_qgain_i,
ctrl_rf2_iqdac_igain_i, ctrl_rf2_iqdac_qgain_i,
ctrl_rf1_iqdac_ctrl_reg, ctrl_rf2_iqdac_ctrl_reg,
ctrl_iqdac_ram_addr_reg, ctrl_iqdac_ram_data_reg,
ctrl_iqdac_ram_write_reg, ctrl_iqdac_ram_play_reg,
ctrl_rf1_dds_ftw_valid_reg, ctrl_rf1_dds_ftw_reg,
ctrl_rf2_dds_ftw_valid_reg, ctrl_rf2_dds_ftw_reg,
ctrl_nco_reset_ctrl_mask_dds_reg,
ctrl_nco_reset_ctrl_mask_rfnco_ch1_reg,
ctrl_nco_reset_ctrl_mask_rfnco_ch2_reg,
ctrl_nco_reset_ctrl_mask_rf1_trig1_reg,
......@@ -4978,6 +5033,23 @@ begin
init_xadc_re <= rd_req_int;
rd_dat_d0 <= init_xadc_i.dat(15 downto 0);
rd_ack_d0 <= init_xadc_rack;
when "00101" =>
case adr_int(7 downto 1) is
when "0000000" =>
-- Reg init_bmctrl_rfframe_ctrl
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= init_bmctrl_rfframe_ctrl_reset_reg;
rd_dat_d0(1) <= init_bmctrl_rfframe_ctrl_en_reg;
rd_dat_d0(2) <= init_bmctrl_rfframe_ctrl_update_i;
rd_dat_d0(15 downto 3) <= (others => '0');
when "0000001" =>
-- Reg init_bmctrl_rfframe_status
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= init_bmctrl_rfframe_status_fifo_rdy_i;
rd_dat_d0(15 downto 1) <= (others => '0');
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
......
hdl/rtl/wr2rf_regs_core.vhd
View file @ 286074c7
......@@ -271,6 +271,11 @@ entity wr2rf_regs_core is
txframe_payload_o : out t_RFmFramePayload;
bmctrl_rfframe_status_fifo_rdy_i : std_logic;
bmctrl_rfframe_ctrl_reset_o : out std_logic;
bmctrl_rfframe_ctrl_en_o : out std_logic;
bmctrl_rfframe_ctrl_update_o : out std_logic;
ila_sigs_o : out std_logic_vector(7 downto 0) );
attribute keep_hierarchy : string;
......@@ -340,6 +345,9 @@ architecture arch of wr2rf_regs_core is
signal txframe_noise : std_logic_vector(31 downto 0);
signal txframe_control : std_logic_vector(15 downto 0);
signal bmctrl_rfframe_ctrl_update : std_logic;
signal bmctrl_rfframe_ctrl_wr : std_logic;
signal reconfigure_wr : std_logic;
signal reconfigure_key : std_logic_vector(15 downto 0);
......@@ -502,6 +510,13 @@ begin
init_xadc_i => xadc_wb_i,
init_xadc_o => xadc_wb_o,
init_bmctrl_rfframe_ctrl_update_i => '0',
init_bmctrl_rfframe_status_fifo_rdy_i => bmctrl_rfframe_status_fifo_rdy_i,
init_bmctrl_rfframe_ctrl_reset_o => bmctrl_rfframe_ctrl_reset_o,
init_bmctrl_rfframe_ctrl_en_o => bmctrl_rfframe_ctrl_en_o,
init_bmctrl_rfframe_ctrl_update_o => bmctrl_rfframe_ctrl_update,
init_bmctrl_rfframe_ctrl_wr_o => bmctrl_rfframe_ctrl_wr,
init_wrpc_i => wb16_wrpc_in,
init_wrpc_o => wb16_wrpc_out,
......@@ -584,6 +599,8 @@ begin
txframe_payload_o <= txframe_payload_r;
-- Update is a pulse.
bmctrl_rfframe_ctrl_update_o <= bmctrl_rfframe_ctrl_update and bmctrl_rfframe_ctrl_wr;
inst_rf_spi: entity work.xwb_spi16
......
hdl/rtl/wr2rf_rfchan.vhd
View file @ 286074c7
......@@ -169,12 +169,12 @@ begin
frev_o => rfnco_frev,
ftw_h1_o => open,
ftw_h1_on_o => open,
ftw_lo_0_i => std_logic_vector'(others => '0'),
ftw_lo_1_i => std_logic_vector'(others => '0'),
ftw_lo_0_i => (others => '0'),
ftw_lo_1_i => (others => '0'),
ftw_valid_o => open,
interlock_o => open,
offset_FSK_i_0 => std_logic_vector'(others => '0'),
offset_i_0 => std_logic_vector'(others => '0'),
offset_FSK_i_0 => (others => '0'),
offset_i_0 => (others => '0'),
phase_h1_comp_o => open,
phase_h1_main_o => open,
phase_h1_o => open,
......
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ 286074c7
......@@ -43,8 +43,8 @@ entity wr2rf_vme is
generic (
g_simulation : integer := 0;
g_dpram_size : integer := 131072/4;
g_dpram_initf : string := "../../../../dependencies/wrpc-sw-file/wrc.bram";
-- g_dpram_initf : string := "";
-- g_dpram_initf : string := "../../../../dependencies/wrpc-sw-file/wrc.bram";
g_dpram_initf : string := "";
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
......@@ -571,6 +571,7 @@ architecture rtl of wr2rf_vme is
signal wrs_tx_TransmitFrame_p1 : std_logic := '0';
signal wrs_tx_RFFrameHeader : t_RFFrameHeader := c_RFFrameHeader_zero;
signal wrs_tx_RFmFramePayloads : t_RFmFramePayload := c_RFmFramePayload_zero;
signal txframe_payload : t_RFmFramePayload;
signal loc_rx_RFmFramePayloads : t_RFmFramePayload;
signal loc_rx_Frame_Valid_pX : std_logic;
signal rx_RFmFramePayloads : t_RFmFramePayload;
......@@ -597,7 +598,6 @@ architecture rtl of wr2rf_vme is
signal loc_nco_h1_prog : std_logic_vector(c_FTW_size-1 downto 0);
signal loc_nco_update_valid : std_logic;
signal loc_or_wrs_params_sel : std_logic;
signal loc_nco_update_valid_r : std_logic;
signal loc_rx_reset_nco_pulse : std_logic;
signal wrs_frame_counter : unsigned(15 downto 0);
......@@ -628,6 +628,20 @@ architecture rtl of wr2rf_vme is
signal wb_rfframerxtx_in : t_wishbone_master_in;
signal wb_rfframerxtx_out : t_wishbone_master_out;
signal rfframe_fifo_din : std_logic_vector(48+16-1 downto 0);
signal rfframe_fifo_dout : std_logic_vector(48+16-1 downto 0);
signal rfframe_fifo_full : std_logic;
signal rfframe_fifo_empty : std_logic;
signal rfframe_fifo_we : std_logic;
signal rfframe_fifo_rd : std_logic;
signal rfframe_fifo_rst_n : std_logic;
signal rfframe_fifo_out_payload : t_RFmFramePayload := c_RFmFramePayload_zero;
signal bmctrl_rfframe_ctrl_update : std_logic;
signal bmctrl_rfframe_ctrl_en : std_logic;
signal bmctrl_rfframe_ctrl_reset : std_logic;
signal bmctrl_rfframe_status_fifo_rdy : std_logic;
signal wb_rf1_rfnco_in : t_wishbone_master_in;
signal wb_rf1_rfnco_out : t_wishbone_master_out;
signal wb_rf2_rfnco_in : t_wishbone_master_in;
......@@ -856,7 +870,7 @@ begin
rx_data_o => phy_rx_data,
rx_k_o => phy_rx_k,
rx_enc_err_o => phy_rx_enc_err,
-- rx_bitslide_o => phy_rx_bitslide,
rx_bitslide_o => open,
rx_rbclk_sampled_o => phy_rx_rbclk_sampled,
rst_i => phy_rst,
loopen_i => phy_loopen,
......@@ -1053,7 +1067,46 @@ begin
wb_slave_i => wb_rfframerxtx_out,
wb_slave_o => wb_rfframerxtx_in );
wrs_tx_RFFrameHeader <= c_RFFrameHeader_dummy;
wrs_tx_RFFrameHeader <= c_RFFrameHeader_dummy;
-- Fifo for playing a ftw sequence.
inst_rfframe_fifo: entity work.generic_sync_fifo
generic map (
g_data_width => 48 + 16,
g_size => 16,
g_show_ahead => True,
g_show_ahead_legacy_mode => False,
g_with_empty => True,
g_with_full => True,
g_with_almost_empty => False,
g_with_almost_full => False,
g_with_count => False
)
port map (
rst_n_i => rfframe_fifo_rst_n,
clk_i => clk_sys_62m5,
d_i => rfframe_fifo_din,
we_i => rfframe_fifo_we,
q_o => rfframe_fifo_dout,
rd_i => rfframe_fifo_rd,
empty_o => rfframe_fifo_empty,
full_o => rfframe_fifo_full,
almost_empty_o => open,
almost_full_o => open,
count_o => open
);
rfframe_fifo_rst_n <= rst_sys_n and not bmctrl_rfframe_ctrl_reset;
rfframe_fifo_din(63 downto 48) <= txframe_payload.control;
rfframe_fifo_din(48-1 downto 0) <= txframe_payload.FTW_H1_main;
rfframe_fifo_we <= bmctrl_rfframe_ctrl_update and not rfframe_fifo_full;
rfframe_fifo_rd <= not rfframe_fifo_empty and bmctrl_rfframe_ctrl_en and rf1_frev_main;
bmctrl_rfframe_status_fifo_rdy <= not rfframe_fifo_full;
rfframe_fifo_out_payload.FTW_H1_main <= rfframe_fifo_dout(47 downto 0);
rfframe_fifo_out_payload.control <= rfframe_fifo_dout(63 downto 48);
wrs_tx_TransmitFrame_p1 <= rfframe_fifo_rd;
wrs_tx_RFmFramePayloads <= rfframe_fifo_out_payload when bmctrl_rfframe_ctrl_en = '1' else txframe_payload;
process (clk_sys_62m5) is
begin
......@@ -1111,12 +1164,11 @@ begin
rfframe_tai <= tm_tai when wrs_frame_valid = '1' else rfframe_tai_r;
rfframe_cycles <= tm_cycles when wrs_frame_valid = '1' else rfframe_cycles_r;
loc_rx_RFmFramePayloads.control(0) <= loc_nco_ctrl_reset;
loc_rx_RFmFramePayloads.FTW_H1_main <= loc_nco_h1_ftw;
loc_rx_RFmFramePayloads.control(0) <= rfframe_fifo_out_payload.control(0) when bmctrl_rfframe_ctrl_en = '1' else loc_nco_ctrl_reset;
loc_rx_RFmFramePayloads.FTW_H1_main <= rfframe_fifo_out_payload.FTW_H1_main when bmctrl_rfframe_ctrl_en = '1' else loc_nco_h1_ftw;
loc_rx_RFmFramePayloads.FTW_H1_prog <= loc_nco_h1_prog;
loc_rx_Frame_valid_pX <= loc_nco_update_valid;
loc_rx_reset_nco_pulse <= '1' when loc_nco_update_valid = '1' else '0';
loc_rx_Frame_valid_pX <= rfframe_fifo_rd when bmctrl_rfframe_ctrl_en = '1' else loc_nco_update_valid;
loc_rx_reset_nco_pulse <= rfframe_fifo_dout(48) and rfframe_fifo_rd when bmctrl_rfframe_ctrl_en = '1' else loc_nco_update_valid;
rx_RFmFramePayloads <= loc_rx_RFmFramePayloads when loc_or_wrs_params_sel = '1' else wrs_rx_RFmFramePayloads;
rx_Frame_valid_pX <= loc_rx_Frame_valid_pX when loc_or_wrs_params_sel = '1' else wrs_rx_Frame_valid_pX;
......@@ -1129,7 +1181,7 @@ begin
nco_reset_rf1_trig1 <= rx_reset_nco_pulse and (not nco_reset_rf1_trig1_mask);
nco_reset_rf2_trig1 <= rx_reset_nco_pulse and (not nco_reset_rf2_trig1_mask);
wr2rf_dds_i : entity work.wr2rf_dds
inst_wr2rf_dds : entity work.wr2rf_dds
port map (
clk62m5_i => clk_sys_62m5,
clk125m_i => clk125m,
......@@ -1167,7 +1219,7 @@ begin
end if;
end process;
wr2rf_rfchan_wrap_i : entity work.wr2rf_rfchan_wrap
inst_wr2rf_rfchan_wrap : entity work.wr2rf_rfchan_wrap
port map (
clk125m_i => clk125m,
clk250m_i => clk250m,
......@@ -1641,7 +1693,7 @@ begin
rfframe_tai_i => rfframe_tai_h,
rfframe_cycles_i => rfframe_cycles_h,
txframe_payload_o => wrs_tx_RFmFramePayloads,
txframe_payload_o => txframe_payload,
nco_reset_dds_mask_o => nco_reset_dds_mask,
nco_reset_rfnco_ch1_mask_o => nco_reset_rfnco_ch1_mask,
......@@ -1695,6 +1747,11 @@ begin
flash_mosi_o => spi_flash_mosi_sys,
flash_sck_o => spi_flash_sck_sys,
bmctrl_rfframe_ctrl_update_o => bmctrl_rfframe_ctrl_update,
bmctrl_rfframe_status_fifo_rdy_i => bmctrl_rfframe_status_fifo_rdy,
bmctrl_rfframe_ctrl_reset_o => bmctrl_rfframe_ctrl_reset,
bmctrl_rfframe_ctrl_en_o => bmctrl_rfframe_ctrl_en,
xadc_wb_i => xadc_wb_in,
xadc_wb_o => xadc_wb_out,
......
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