vtuCore: reorder ports, add comments.

1df96bbf · Tristan Gingold · 939c553d · 1df96bbf
Commit 1df96bbf authored May 04, 2020 by Tristan Gingold
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Showing with 26 additions and 19 deletions

vtuCore.vhd dependencies/vtu/rtl/vtuCore.vhd +26 -19

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--- a/dependencies/vtu/rtl/vtuCore.vhd
+++ b/dependencies/vtu/rtl/vtuCore.vhd
@@ -886,13 +886,20 @@ use work.MemMap_ctuAsVtu.all;
 entity vtuCore is
  port (
-    --  Interface to the memory for the play memory mode.
+        Clk : in std_logic;
-        Mem_RdDone : in std_logic;
+        Rst : in std_logic; --  Synchronous to QCLk
-        Mem_Addr : out std_logic_vector(14 downto 0 );
-        Mem_RdData : in std_logic_vector(7 downto 0 );
+        --  Inputs.
-        Mem_RdEna : out std_logic;
+        Start : in std_logic;
+        Stop : in std_logic;
+        --  Sync input.
+        DataIn : in std_logic_vector(7 downto 0 );
+        --  Output.
+        DataOut : out std_logic_vector(7 downto 0 );
-        --  Mode:
+        --  Mode Parameter:
        --   000: single pulse
        --   001: infinite window
        --   010: windowed operation,
@@ -906,35 +913,35 @@ entity vtuCore is
        bValue : in std_logic_vector(63 downto 0 );
        wrongB : out std_logic;
-        --  Parameter: first synchronize with sync (?)
-        UseSyncAsStart : in std_logic;
        --  Parameter: number of pulses
        htValue : in std_logic_vector(63 downto 0 );
-        htSwitching : in std_logic;
        wrongHT : out std_logic;
        --  Parameter: window size
        wValue : in std_logic_vector(63 downto 0 );
        wrongW : out std_logic;
-        --  Inputs.
+        --  Parameter: first synchronize with sync (?)
-        Start : in std_logic;
+        UseSyncAsStart : in std_logic;
-        Stop : in std_logic;
-        DataIn : in std_logic_vector(7 downto 0 );
+        --  Switch between htValue and htValue-1.
+        htSwitching : in std_logic;
-        --  Output.
+        --  Interface to the memory for the play memory mode.
-        DataOut : out std_logic_vector(7 downto 0 );
+        Mem_RdDone : in std_logic;
+        Mem_Addr : out std_logic_vector(14 downto 0 );
+        Mem_RdData : in std_logic_vector(7 downto 0 );
+        Mem_RdEna : out std_logic;
        --  Parameter: position of the last bit to be played.
        Mem_LastBit : in std_logic_vector(2 downto 0 );
        Mem_LastElem : in std_logic_vector(14 downto 0 );
+        --  A pulse has been detected on DataIn.
        SyncPulse : out std_logic;
-        Rst : in std_logic;--  Synchronous to QCLk
-        Run : out std_logic;
+        --  The VTU is running.
-        Clk : in std_logic
+        Run : out std_logic
        );
 end vtuCore;