wr2rf_init_regs.cheby: 10m and pps are inputs on reset

115b1544 · Tristan Gingold · f1e60649 · 115b1544 · 115b1544
Commit 115b1544 authored Jun 12, 2023 by Tristan Gingold
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wr2rf_init_regs.cheby hdl/rtl/registers/wr2rf_init_regs.cheby +2 -2

wr2rf_vme_regs.vhd hdl/rtl/registers/wr2rf_vme_regs.vhd +6 -3

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--- a/hdl/rtl/registers/wr2rf_init_regs.cheby
+++ b/hdl/rtl/registers/wr2rf_init_regs.cheby
@@ -308,13 +308,13 @@ memory-map:
      - field:
         name: ext_10m_dir
         description: direction of the 10Mhz clock front panel  connector
-         preset: 1
+         preset: 0
         comment: "0: input, 1 : output"
         range: 0
      - field:
         name: ext_pps_dir
         description: direction of pps front panel connector
-         preset: 1
+         preset: 0
         comment: "0: input, 1 : output"
         range: 1
  - reg:

--- a/hdl/rtl/registers/wr2rf_vme_regs.vhd
+++ b/hdl/rtl/registers/wr2rf_vme_regs.vhd
 -- Do not edit.  Generated by cheby 1.6.dev0 using these options:
 --  -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
-- Generated on Fri May 12 13:30:55 2023 by tgingold
+-- Generated on Mon Jun 12 08:33:57 2023 by tgingold


 library ieee;
@@ -367,8 +367,11 @@ entity wr2rf_vme_regs is
    init_xadc_o          : out   t_wishbone_master_out;

    -- REG ctrl
+    -- Reset fifo
    init_bmctrl_rfframe_ctrl_reset_o : out   std_logic;
+    -- Enable playing from the fifo
    init_bmctrl_rfframe_ctrl_en_o : out   std_logic;
+    -- Write txframe to the fifo
    init_bmctrl_rfframe_ctrl_update_i : in    std_logic;
    init_bmctrl_rfframe_ctrl_update_o : out   std_logic;
    init_bmctrl_rfframe_ctrl_wr_o : out   std_logic;
@@ -1366,8 +1369,8 @@ begin
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
-        init_pin_ctrl_ext_10m_dir_reg <= '1';
-        init_pin_ctrl_ext_pps_dir_reg <= '1';
+        init_pin_ctrl_ext_10m_dir_reg <= '0';
+        init_pin_ctrl_ext_pps_dir_reg <= '0';
        init_pin_ctrl_wack <= '0';
      else
        if init_pin_ctrl_wreq = '1' then