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Commit 1110276b authored by Tristan Gingold's avatar Tristan Gingold
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vtuCore: simplify vtudatashifter.

parent b7dfe48d
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dependencies/vtu/rtl/vtuCore.vhd
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......@@ -543,26 +543,19 @@ architecture vtuDataShifter of vtuDataShifter is
signal DataClean : std_logic_vector(7 downto 0 );
signal DataOut_i : std_logic_vector(7 downto 0 );
signal CoarseCnt : std_logic_vector(N - 4 downto 0 );
signal Next_CoarseCnt : std_logic_vector(N - 4 downto 0 );
signal ClearOutGoodNext : std_logic;
signal CZeroDly : std_logic_vector(N - 4 downto 0 );
signal C_Zero8 : std_logic_vector(7 downto 0 );
signal Ready : std_logic;
signal CoarseGood : std_logic;
signal OutGoodNext : std_logic;
signal DataIn_clean : std_logic_vector(7 downto 0 );
signal OutMuxSel : std_logic;
signal Sync_prev : std_logic;
signal CoarseDly : std_logic_vector(N - 4 downto 0 );
signal OutputEnabled_i : std_logic;
signal CntRst : std_logic;
signal CoarseDly_i : std_logic_vector(N - 4 downto 0 );
signal Sync_i : std_logic;
signal OutGood : std_logic;
signal COne : std_logic_vector(N - 4 downto 0 );
signal Disabled : std_logic;
signal DataRaw : std_logic_vector(15 downto 0 );
signal CoarseZero_i : std_logic;
signal RemoveDoubleSync : std_logic;
signal UseNextValue : std_logic;
signal FineDly : std_logic_vector(2 downto 0 );
component RSFF
......@@ -574,146 +567,107 @@ architecture vtuDataShifter of vtuDataShifter is
Q : out std_logic
);
end component;
signal visual_B_CoarseDly_sub_dif_int : std_logic_vector((N - 4) + 1 downto 0 );
signal visual_B_CoarseDly_sub_tmp_a : std_logic_vector((N - 4) + 1 - 1 downto 0 );
signal visual_B_CoarseDly_sub_tmp_b : std_logic_vector((N - 4) + 1 - 1 downto 0 );
constant visual_B_CoarseDly_sub_zero : std_logic_vector((N - 4) + 1 - 1 downto 0 ) := (others => '0');
begin
B_ReadyFF: RSFF
port map (Clk => Clk,
Set => SyncPulse_i,
Clr => Disabled,
Rst => open,
Q => Ready);
-- Detect the sync pulse.
b_sync_pulse: block
begin
-- Set if at least one bit is set.
Sync_i <= '1' when DataIn /= b"0000_0000" else '0';
B_OutGoodNext: RSFF
port map (Clk => Clk,
Set => OutGood,
Clr => ClearOutGoodNext,
Rst => open,
Q => OutGoodNext);
-- Filter out long pulses or very close pulses.
SyncPulse_i <= (not (g_DisableDoubleSync and Sync_prev)) and Sync_i;
DataIn_clean <= clean_data(DataIn);
SyncPulse <= SyncPulse_i;
-- Set if at least one bit is set.
Sync_i <= '1' when DataIn /= b"0000_0000" else '0';
process (Clk)
begin
if (Clk'event and Clk = '1') then
Sync_prev <= Sync_i;
end if;
end process;
end block;
-- Capture the data containing the pulse.
-- Clean to have only one bit set (so a real pulse)
process (Clk)
begin
if (Clk'event and Clk = '1') then
if CntRst = '1' then
CoarseCnt <= (others => '0');
else
CoarseCnt <= std_logic_vector(unsigned (CoarseCnt) + 1);
if SyncPulse_i = '1' then
DataClean <= clean_data(DataIn);
end if;
end if;
end process;
CoarseDly_i(N-4 downto 0) <= Delay(N-1 downto 3);
FineDly(2 downto 0) <= Delay(2 downto 0);
-- Set Ready: when a pulse has been detected.
B_ReadyFF: entity work.RSFF
port map (Clk => Clk,
Set => SyncPulse_i,
Clr => Disabled,
Rst => open,
Q => Ready);
CntRst <= ( SyncPulse_i) or ( Disabled);
-- Split Delay into coarse and fine delay.
CoarseDly <= Delay(N-1 downto 3);
FineDly <= Delay(2 downto 0);
process (C_Zero8, DataOut_i, OutputEnabled_i)
begin
case OutputEnabled_i is
when '0' =>
DataOut(7 downto 0) <= C_Zero8(7 downto 0);
when others =>
DataOut(7 downto 0) <= DataOut_i(7 downto 0);
end case;
end process;
-- True when Coarse is zero.
CoarseZero_i <= '1' when CoarseDly = (N-4 downto 0 => '0') else '0';
CoarseZero <= CoarseZero_i;
process (CoarseCnt, CoarseDly)
begin
if CoarseCnt(N-4 downto 0) = CoarseDly(N-4 downto 0) then
CoarseGood <= '1';
else
CoarseGood <= '0';
end if;
end process;
-- Shift is disabled if not enabled or if Delay is less than 1 coarse cycle.
Disabled <= (not Enabled) or CoarseZero_i;
-- Coarse counter.
process (Clk)
begin
if (Clk'event and Clk = '1') then
if SyncPulse_i = '1' then
DataClean(7 downto 0) <= (DataIn_clean(7 downto 0));
if rising_edge (Clk) then
if SyncPulse_i = '1' or Disabled = '1' then
-- Start count at sync pulse.
CoarseCnt <= (others => '0');
else
CoarseCnt <= Next_CoarseCnt;
end if;
end if;
end process;
Next_CoarseCnt <= std_logic_vector(unsigned (CoarseCnt) + 1);
process (OutGood, OutGoodNext, UseNextValue)
begin
case UseNextValue is
when '0' =>
OutMuxSel <= OutGood;
when others =>
OutMuxSel <= OutGoodNext;
end case;
end process;
-- Set when data output is to be generated for this cycle.
OutGood <= Ready when Next_CoarseCnt = CoarseDly else '0';
ShiftReg_proc: process (DataRaw, FineDly)
variable DataOut_aux : std_logic_vector(15 downto 0);
begin
DataOut_aux(15 downto 0) := std_logic_vector(shift_right(unsigned(DataRaw), to_integer(unsigned(FineDly))));
UseNextValue <= or_reduce(DataOut_aux(7 downto 0));
if or_reduce(DataOut_aux(7 downto 0)) = '0' then
DataOut_i(7 downto 0) <= DataOut_aux(15 downto 8);
else
DataOut_i(7 downto 0) <= DataOut_aux(7 downto 0);
end if;
end process;
B_OutGoodNext: RSFF
port map (Clk => Clk,
Set => OutGood,
Clr => ClearOutGoodNext,
Rst => open,
Q => OutGoodNext);
DataRaw(15 downto 8) <= DataClean(7 downto 0);
DataRaw(7 downto 0) <= C_Zero8(7 downto 0);
-- Maybe OutGood must be delayed by 1 cycle due to fine delay.
OutMuxSel <= OutGoodNext when UseNextValue = '1' else OutGood;
C_Zero8(7 downto 0) <= (others => '0');
OutputEnabled_i <= OutMuxSel and (not Disabled);
OutputEnabled <= OutputEnabled_i;
SyncPulse <= SyncPulse_i;
DataRaw(15 downto 8) <= DataClean;
DataRaw(7 downto 0) <= (others => '0');
process (Clk)
-- Prepare next data output.
ShiftReg_proc: process (DataRaw, FineDly)
variable DataOut_aux : std_logic_vector(15 downto 0);
begin
if (Clk'event and Clk = '1') then
Sync_prev <= Sync_i;
DataOut_aux := std_logic_vector(shift_right(unsigned(DataRaw), to_integer(unsigned(FineDly))));
if DataOut_aux(7 downto 0) = (7 downto 0 => '0') then
DataOut_i <= DataOut_aux(15 downto 8);
-- Need to wait one cycle.
UseNextValue <= '0';
else
DataOut_i <= DataOut_aux(7 downto 0);
UseNextValue <= '1';
end if;
end process;
OutGood <= CoarseGood and Ready;
process (CoarseDly_i, CZeroDly)
begin
if CoarseDly_i(N-4 downto 0) = CZeroDly(N-4 downto 0) then
CoarseZero_i <= '1';
else
CoarseZero_i <= '0';
end if;
end process;
CZeroDly(N-4 downto 0) <= (others => '0');
Disabled <= (not Enabled) or ( CoarseZero_i);
visual_B_CoarseDly_sub_tmp_a <= (CoarseDly_i(N-4 downto 0));
visual_B_CoarseDly_sub_tmp_b <= (COne(N-4 downto 0));
visual_B_CoarseDly_sub_dif_int <= std_logic_vector
((unsigned('0' & visual_B_CoarseDly_sub_tmp_a) - unsigned('0' & visual_B_CoarseDly_sub_tmp_b)));
CoarseDly(N-4 downto 0) <= visual_B_CoarseDly_sub_dif_int((N-4) + 1 - 1 downto 0);
COne(N-4 downto 0) <= (0=>'1', others=>'0');
SyncPulse_i <= ((not RemoveDoubleSync) or (not Sync_prev)) and Sync_i;
DataOut <= DataOut_i when OutputEnabled_i = '1' else (others => '0');
ClearOutGoodNext <= (not UseNextValue) or Disabled or OutGoodNext;
OutputEnabled_i <= OutMuxSel and (not Disabled);
CoarseZero <= CoarseZero_i;
RemoveDoubleSync <= g_DisableDoubleSync;
OutputEnabled <= OutputEnabled_i;
end vtuDataShifter;
library ieee;
......
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