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wr2rf-vme
Commit 08d1bc0b authored by John Gill's avatar John Gill
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Added registers for atomic updates to iqdac IQ amplitude and phase functions.

parent bf56e518
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Showing with 421 additions and 119 deletions
hdl/rtl/registers/trigunit_regs.vhd
View file @ 08d1bc0b
-- Do not edit. Generated on Fri Apr 16 10:16:55 2021 by jgill
-- Do not edit. Generated on Wed Sep 01 09:30:11 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
......
hdl/rtl/registers/wr2rf_ctrl_regs.cheby
View file @ 08d1bc0b
......@@ -25,25 +25,79 @@ memory-map:
size: 4096
x-hdl:
busgroup: true
- reg:
name: rf1_iqdac_phase
description: phase represented as a signed integer
access: rw
width: 16
- reg:
name: rf2_iqdac_phase
description: phase represented as a signed integer
access: rw
width: 16
- reg:
name: rf1_iqdac_phase_update
description: phase represented as a signed integer
access: rw
width: 16
children:
- field:
name: valid
range: 0
preset: 0
x-hdl:
type: autoclear
- reg:
name: rf2_iqdac_phase_update
description: phase represented as a signed integer
access: rw
width: 16
children:
- field:
name: valid
range: 0
preset: 0
x-hdl:
type: autoclear
- reg:
name: rf1_iqdac_igain_arm
description: I ampl/phase for IQ complex multiplier
access: rw
width: 16
- reg:
name: rf1_iqdac_qgain_arm
description: Q ampl/phase for IQ complex multiplier
access: rw
width: 16
- reg:
name: rf2_iqdac_igain_arm
description: I ampl/phase for IQ complex multiplier
access: rw
width: 16
- reg:
name: rf2_iqdac_qgain_arm
description: Q ampl/phase for IQ complex multiplier
access: rw
width: 16
- reg:
name: rf1_iqdac_igain
description: I gain for IQ complex multiplier
access: rw
access: ro
width: 16
- reg:
name: rf1_iqdac_qgain
description: I gain for IQ complex multiplier
access: rw
access: ro
width: 16
- reg:
name: rf2_iqdac_igain
description: I gain for IQ complex multiplier
access: rw
access: ro
width: 16
- reg:
name: rf2_iqdac_qgain
description: I gain for IQ complex multiplier
access: rw
access: ro
width: 16
- reg:
name: rf1_iqdac_ctrl
......
hdl/rtl/registers/wr2rf_init_rf_regs.vhd
View file @ 08d1bc0b
-- Do not edit. Generated on Fri Apr 16 10:16:56 2021 by jgill
-- Do not edit. Generated on Wed Sep 01 09:30:11 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
......
hdl/rtl/registers/wr2rf_rfnco_regs.vhd
View file @ 08d1bc0b
-- Do not edit. Generated on Fri Apr 16 10:16:57 2021 by jgill
-- Do not edit. Generated on Wed Sep 01 09:30:12 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i RFNCO.cheby --gen-hdl
......
hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
View file @ 08d1bc0b
-- Do not edit. Generated on Fri Apr 16 10:16:56 2021 by jgill
-- Do not edit. Generated on Wed Sep 01 09:30:11 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......
hdl/rtl/registers/wr2rf_vme_regs.vhd
View file @ 08d1bc0b
-- Do not edit. Generated on Fri Apr 16 10:16:58 2021 by jgill
-- Do not edit. Generated on Wed Sep 01 09:30:13 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
......@@ -367,17 +367,41 @@ entity wr2rf_vme_regs is
ctrl_rf2_rfnco_i : in t_wishbone_master_in;
ctrl_rf2_rfnco_o : out t_wishbone_master_out;
-- phase represented as a signed integer
ctrl_rf1_iqdac_phase_o : out std_logic_vector(15 downto 0);
-- phase represented as a signed integer
ctrl_rf2_iqdac_phase_o : out std_logic_vector(15 downto 0);
-- phase represented as a signed integer
ctrl_rf1_iqdac_phase_update_valid_o : out std_logic;
-- phase represented as a signed integer
ctrl_rf2_iqdac_phase_update_valid_o : out std_logic;
-- I ampl/phase for IQ complex multiplier
ctrl_rf1_iqdac_igain_arm_o : out std_logic_vector(15 downto 0);
-- Q ampl/phase for IQ complex multiplier
ctrl_rf1_iqdac_qgain_arm_o : out std_logic_vector(15 downto 0);
-- I ampl/phase for IQ complex multiplier
ctrl_rf2_iqdac_igain_arm_o : out std_logic_vector(15 downto 0);
-- Q ampl/phase for IQ complex multiplier
ctrl_rf2_iqdac_qgain_arm_o : out std_logic_vector(15 downto 0);
-- I gain for IQ complex multiplier
ctrl_rf1_iqdac_igain_o : out std_logic_vector(15 downto 0);
ctrl_rf1_iqdac_igain_i : in std_logic_vector(15 downto 0);
-- I gain for IQ complex multiplier
ctrl_rf1_iqdac_qgain_o : out std_logic_vector(15 downto 0);
ctrl_rf1_iqdac_qgain_i : in std_logic_vector(15 downto 0);
-- I gain for IQ complex multiplier
ctrl_rf2_iqdac_igain_o : out std_logic_vector(15 downto 0);
ctrl_rf2_iqdac_igain_i : in std_logic_vector(15 downto 0);
-- I gain for IQ complex multiplier
ctrl_rf2_iqdac_qgain_o : out std_logic_vector(15 downto 0);
ctrl_rf2_iqdac_qgain_i : in std_logic_vector(15 downto 0);
-- Select iqdac I + Q sources
ctrl_rf1_iqdac_ctrl_o : out std_logic_vector(15 downto 0);
......@@ -704,18 +728,30 @@ architecture syn of wr2rf_vme_regs is
signal ctrl_rf2_rfnco_tr : std_logic;
signal ctrl_rf2_rfnco_wack : std_logic;
signal ctrl_rf2_rfnco_rack : std_logic;
signal ctrl_rf1_iqdac_igain_reg : std_logic_vector(15 downto 0);
signal ctrl_rf1_iqdac_igain_wreq : std_logic;
signal ctrl_rf1_iqdac_igain_wack : std_logic;
signal ctrl_rf1_iqdac_qgain_reg : std_logic_vector(15 downto 0);
signal ctrl_rf1_iqdac_qgain_wreq : std_logic;
signal ctrl_rf1_iqdac_qgain_wack : std_logic;
signal ctrl_rf2_iqdac_igain_reg : std_logic_vector(15 downto 0);
signal ctrl_rf2_iqdac_igain_wreq : std_logic;
signal ctrl_rf2_iqdac_igain_wack : std_logic;
signal ctrl_rf2_iqdac_qgain_reg : std_logic_vector(15 downto 0);
signal ctrl_rf2_iqdac_qgain_wreq : std_logic;
signal ctrl_rf2_iqdac_qgain_wack : std_logic;
signal ctrl_rf1_iqdac_phase_reg : std_logic_vector(15 downto 0);
signal ctrl_rf1_iqdac_phase_wreq : std_logic;
signal ctrl_rf1_iqdac_phase_wack : std_logic;
signal ctrl_rf2_iqdac_phase_reg : std_logic_vector(15 downto 0);
signal ctrl_rf2_iqdac_phase_wreq : std_logic;
signal ctrl_rf2_iqdac_phase_wack : std_logic;
signal ctrl_rf1_iqdac_phase_update_valid_reg : std_logic;
signal ctrl_rf1_iqdac_phase_update_wreq : std_logic;
signal ctrl_rf1_iqdac_phase_update_wack : std_logic;
signal ctrl_rf2_iqdac_phase_update_valid_reg : std_logic;
signal ctrl_rf2_iqdac_phase_update_wreq : std_logic;
signal ctrl_rf2_iqdac_phase_update_wack : std_logic;
signal ctrl_rf1_iqdac_igain_arm_reg : std_logic_vector(15 downto 0);
signal ctrl_rf1_iqdac_igain_arm_wreq : std_logic;
signal ctrl_rf1_iqdac_igain_arm_wack : std_logic;
signal ctrl_rf1_iqdac_qgain_arm_reg : std_logic_vector(15 downto 0);
signal ctrl_rf1_iqdac_qgain_arm_wreq : std_logic;
signal ctrl_rf1_iqdac_qgain_arm_wack : std_logic;
signal ctrl_rf2_iqdac_igain_arm_reg : std_logic_vector(15 downto 0);
signal ctrl_rf2_iqdac_igain_arm_wreq : std_logic;
signal ctrl_rf2_iqdac_igain_arm_wack : std_logic;
signal ctrl_rf2_iqdac_qgain_arm_reg : std_logic_vector(15 downto 0);
signal ctrl_rf2_iqdac_qgain_arm_wreq : std_logic;
signal ctrl_rf2_iqdac_qgain_arm_wack : std_logic;
signal ctrl_rf1_iqdac_ctrl_reg : std_logic_vector(15 downto 0);
signal ctrl_rf1_iqdac_ctrl_wreq : std_logic;
signal ctrl_rf1_iqdac_ctrl_wack : std_logic;
......@@ -2185,70 +2221,146 @@ begin
ctrl_rf2_rfnco_o.we <= ctrl_rf2_rfnco_wt;
ctrl_rf2_rfnco_o.dat(15 downto 0) <= wr_dat_d0;
-- Register ctrl_rf1_iqdac_igain
ctrl_rf1_iqdac_igain_o <= ctrl_rf1_iqdac_igain_reg;
-- Register ctrl_rf1_iqdac_phase
ctrl_rf1_iqdac_phase_o <= ctrl_rf1_iqdac_phase_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ctrl_rf1_iqdac_igain_reg <= "0000000000000000";
ctrl_rf1_iqdac_igain_wack <= '0';
ctrl_rf1_iqdac_phase_reg <= "0000000000000000";
ctrl_rf1_iqdac_phase_wack <= '0';
else
if ctrl_rf1_iqdac_igain_wreq = '1' then
ctrl_rf1_iqdac_igain_reg <= wr_dat_d0;
if ctrl_rf1_iqdac_phase_wreq = '1' then
ctrl_rf1_iqdac_phase_reg <= wr_dat_d0;
end if;
ctrl_rf1_iqdac_igain_wack <= ctrl_rf1_iqdac_igain_wreq;
ctrl_rf1_iqdac_phase_wack <= ctrl_rf1_iqdac_phase_wreq;
end if;
end if;
end process;
-- Register ctrl_rf1_iqdac_qgain
ctrl_rf1_iqdac_qgain_o <= ctrl_rf1_iqdac_qgain_reg;
-- Register ctrl_rf2_iqdac_phase
ctrl_rf2_iqdac_phase_o <= ctrl_rf2_iqdac_phase_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ctrl_rf1_iqdac_qgain_reg <= "0000000000000000";
ctrl_rf1_iqdac_qgain_wack <= '0';
ctrl_rf2_iqdac_phase_reg <= "0000000000000000";
ctrl_rf2_iqdac_phase_wack <= '0';
else
if ctrl_rf1_iqdac_qgain_wreq = '1' then
ctrl_rf1_iqdac_qgain_reg <= wr_dat_d0;
if ctrl_rf2_iqdac_phase_wreq = '1' then
ctrl_rf2_iqdac_phase_reg <= wr_dat_d0;
end if;
ctrl_rf1_iqdac_qgain_wack <= ctrl_rf1_iqdac_qgain_wreq;
ctrl_rf2_iqdac_phase_wack <= ctrl_rf2_iqdac_phase_wreq;
end if;
end if;
end process;
-- Register ctrl_rf2_iqdac_igain
ctrl_rf2_iqdac_igain_o <= ctrl_rf2_iqdac_igain_reg;
-- Register ctrl_rf1_iqdac_phase_update
ctrl_rf1_iqdac_phase_update_valid_o <= ctrl_rf1_iqdac_phase_update_valid_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ctrl_rf2_iqdac_igain_reg <= "0000000000000000";
ctrl_rf2_iqdac_igain_wack <= '0';
ctrl_rf1_iqdac_phase_update_valid_reg <= '0';
ctrl_rf1_iqdac_phase_update_wack <= '0';
else
if ctrl_rf2_iqdac_igain_wreq = '1' then
ctrl_rf2_iqdac_igain_reg <= wr_dat_d0;
if ctrl_rf1_iqdac_phase_update_wreq = '1' then
ctrl_rf1_iqdac_phase_update_valid_reg <= wr_dat_d0(0);
else
ctrl_rf1_iqdac_phase_update_valid_reg <= '0';
end if;
ctrl_rf2_iqdac_igain_wack <= ctrl_rf2_iqdac_igain_wreq;
ctrl_rf1_iqdac_phase_update_wack <= ctrl_rf1_iqdac_phase_update_wreq;
end if;
end if;
end process;
-- Register ctrl_rf2_iqdac_qgain
ctrl_rf2_iqdac_qgain_o <= ctrl_rf2_iqdac_qgain_reg;
-- Register ctrl_rf2_iqdac_phase_update
ctrl_rf2_iqdac_phase_update_valid_o <= ctrl_rf2_iqdac_phase_update_valid_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ctrl_rf2_iqdac_qgain_reg <= "0000000000000000";
ctrl_rf2_iqdac_qgain_wack <= '0';
ctrl_rf2_iqdac_phase_update_valid_reg <= '0';
ctrl_rf2_iqdac_phase_update_wack <= '0';
else
if ctrl_rf2_iqdac_qgain_wreq = '1' then
ctrl_rf2_iqdac_qgain_reg <= wr_dat_d0;
if ctrl_rf2_iqdac_phase_update_wreq = '1' then
ctrl_rf2_iqdac_phase_update_valid_reg <= wr_dat_d0(0);
else
ctrl_rf2_iqdac_phase_update_valid_reg <= '0';
end if;
ctrl_rf2_iqdac_qgain_wack <= ctrl_rf2_iqdac_qgain_wreq;
ctrl_rf2_iqdac_phase_update_wack <= ctrl_rf2_iqdac_phase_update_wreq;
end if;
end if;
end process;
-- Register ctrl_rf1_iqdac_igain_arm
ctrl_rf1_iqdac_igain_arm_o <= ctrl_rf1_iqdac_igain_arm_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ctrl_rf1_iqdac_igain_arm_reg <= "0000000000000000";
ctrl_rf1_iqdac_igain_arm_wack <= '0';
else
if ctrl_rf1_iqdac_igain_arm_wreq = '1' then
ctrl_rf1_iqdac_igain_arm_reg <= wr_dat_d0;
end if;
ctrl_rf1_iqdac_igain_arm_wack <= ctrl_rf1_iqdac_igain_arm_wreq;
end if;
end if;
end process;
-- Register ctrl_rf1_iqdac_qgain_arm
ctrl_rf1_iqdac_qgain_arm_o <= ctrl_rf1_iqdac_qgain_arm_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ctrl_rf1_iqdac_qgain_arm_reg <= "0000000000000000";
ctrl_rf1_iqdac_qgain_arm_wack <= '0';
else
if ctrl_rf1_iqdac_qgain_arm_wreq = '1' then
ctrl_rf1_iqdac_qgain_arm_reg <= wr_dat_d0;
end if;
ctrl_rf1_iqdac_qgain_arm_wack <= ctrl_rf1_iqdac_qgain_arm_wreq;
end if;
end if;
end process;
-- Register ctrl_rf2_iqdac_igain_arm
ctrl_rf2_iqdac_igain_arm_o <= ctrl_rf2_iqdac_igain_arm_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ctrl_rf2_iqdac_igain_arm_reg <= "0000000000000000";
ctrl_rf2_iqdac_igain_arm_wack <= '0';
else
if ctrl_rf2_iqdac_igain_arm_wreq = '1' then
ctrl_rf2_iqdac_igain_arm_reg <= wr_dat_d0;
end if;
ctrl_rf2_iqdac_igain_arm_wack <= ctrl_rf2_iqdac_igain_arm_wreq;
end if;
end if;
end process;
-- Register ctrl_rf2_iqdac_qgain_arm
ctrl_rf2_iqdac_qgain_arm_o <= ctrl_rf2_iqdac_qgain_arm_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ctrl_rf2_iqdac_qgain_arm_reg <= "0000000000000000";
ctrl_rf2_iqdac_qgain_arm_wack <= '0';
else
if ctrl_rf2_iqdac_qgain_arm_wreq = '1' then
ctrl_rf2_iqdac_qgain_arm_reg <= wr_dat_d0;
end if;
ctrl_rf2_iqdac_qgain_arm_wack <= ctrl_rf2_iqdac_qgain_arm_wreq;
end if;
end if;
end process;
-- Register ctrl_rf1_iqdac_igain
-- Register ctrl_rf1_iqdac_qgain
-- Register ctrl_rf2_iqdac_igain
-- Register ctrl_rf2_iqdac_qgain
-- Register ctrl_rf1_iqdac_ctrl
ctrl_rf1_iqdac_ctrl_o <= ctrl_rf1_iqdac_ctrl_reg;
process (clk_i) begin
......@@ -2461,7 +2573,7 @@ begin
end process;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, init_hwinfo_echo_wack, init_fw_update_wack, init_clock_ctrl_wack, init_wrcore_ctrl_wack, init_iodelay_ctrl_wack, init_mmcm_shift_wack, init_tmg_wack, init_lemo_rf1_t1_start_wack, init_lemo_rf1_t2_start_wack, init_lemo_rf2_t1_start_wack, init_lemo_rf2_t2_start_wack, init_lemo_rf1_t1_stop_wack, init_lemo_rf1_t2_stop_wack, init_lemo_rf2_t1_stop_wack, init_lemo_rf2_t2_stop_wack, init_tmgio1_wack, init_tmgio2_wack, init_tmgio3_wack, init_tmgio4_wack, init_tmgclk1_wack, init_tmgclk2_wack, init_lemo_wack, init_lemo_ext_wack, init_softstart_wack, init_softstop_wack, init_lemo_pulse_wack, init_pin_ctrl_wack, init_pll_ctrl_wack, init_dds_ctrl_wack, init_dds_ioupdate_wack, init_ocxo_ctrl_wack, init_nco_azimuthal_wack, init_nco_cabledelay_wack, init_nco_hb_wack, init_nco_h1_ftw_wack, init_nco_h1_prog_wack, init_nco_ctrl_wack, init_nco_update_wack, init_nco_loc_or_wrs_wack, init_svec_mup_ctrl_wack, init_svec_mup_rftrig_wack, init_svec_mup_fmc1_wack, init_svec_mup_fmc2_wack, init_wrc_page0_wack, init_wrc_page1_wack, init_txframe_ftw_h1_main_wack, init_txframe_ftw_h1_prog_wack, init_txframe_ftw_h1_on_wack, init_txframe_dftw_h1_slip1_wack, init_txframe_dftw_h1_slip2_wack, init_txframe_setpoint1_wack, init_txframe_setpoint2_wack, init_txframe_setpoint3_wack, init_txframe_setpoint4_wack, init_txframe_setpoint5_wack, init_txframe_setpoint6_wack, init_txframe_setpoint7_wack, init_txframe_setpoint8_wack, init_txframe_noise_wack, init_txframe_control_wack, init_pll_spi_wack, init_rf_spi_wack, init_rf_wack, init_framerxtx_wack, init_wrpc_wack, ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_rf1_rfnco_wack, ctrl_rf2_rfnco_wack, ctrl_rf1_iqdac_igain_wack, ctrl_rf1_iqdac_qgain_wack, ctrl_rf2_iqdac_igain_wack, ctrl_rf2_iqdac_qgain_wack, ctrl_rf1_iqdac_ctrl_wack, ctrl_rf2_iqdac_ctrl_wack, ctrl_iqdac_ram_addr_wack, ctrl_iqdac_ram_data_wack, ctrl_iqdac_ram_write_wack, ctrl_iqdac_ram_play_wack, ctrl_rf1_dds_ftw_valid_wack, ctrl_rf1_dds_ftw_wack, ctrl_rf2_dds_ftw_valid_wack, ctrl_rf2_dds_ftw_wack, ctrl_nco_reset_ctrl_wack) begin
process (wr_adr_d0, wr_req_d0, init_hwinfo_echo_wack, init_fw_update_wack, init_clock_ctrl_wack, init_wrcore_ctrl_wack, init_iodelay_ctrl_wack, init_mmcm_shift_wack, init_tmg_wack, init_lemo_rf1_t1_start_wack, init_lemo_rf1_t2_start_wack, init_lemo_rf2_t1_start_wack, init_lemo_rf2_t2_start_wack, init_lemo_rf1_t1_stop_wack, init_lemo_rf1_t2_stop_wack, init_lemo_rf2_t1_stop_wack, init_lemo_rf2_t2_stop_wack, init_tmgio1_wack, init_tmgio2_wack, init_tmgio3_wack, init_tmgio4_wack, init_tmgclk1_wack, init_tmgclk2_wack, init_lemo_wack, init_lemo_ext_wack, init_softstart_wack, init_softstop_wack, init_lemo_pulse_wack, init_pin_ctrl_wack, init_pll_ctrl_wack, init_dds_ctrl_wack, init_dds_ioupdate_wack, init_ocxo_ctrl_wack, init_nco_azimuthal_wack, init_nco_cabledelay_wack, init_nco_hb_wack, init_nco_h1_ftw_wack, init_nco_h1_prog_wack, init_nco_ctrl_wack, init_nco_update_wack, init_nco_loc_or_wrs_wack, init_svec_mup_ctrl_wack, init_svec_mup_rftrig_wack, init_svec_mup_fmc1_wack, init_svec_mup_fmc2_wack, init_wrc_page0_wack, init_wrc_page1_wack, init_txframe_ftw_h1_main_wack, init_txframe_ftw_h1_prog_wack, init_txframe_ftw_h1_on_wack, init_txframe_dftw_h1_slip1_wack, init_txframe_dftw_h1_slip2_wack, init_txframe_setpoint1_wack, init_txframe_setpoint2_wack, init_txframe_setpoint3_wack, init_txframe_setpoint4_wack, init_txframe_setpoint5_wack, init_txframe_setpoint6_wack, init_txframe_setpoint7_wack, init_txframe_setpoint8_wack, init_txframe_noise_wack, init_txframe_control_wack, init_pll_spi_wack, init_rf_spi_wack, init_rf_wack, init_framerxtx_wack, init_wrpc_wack, ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_rf1_rfnco_wack, ctrl_rf2_rfnco_wack, ctrl_rf1_iqdac_phase_wack, ctrl_rf2_iqdac_phase_wack, ctrl_rf1_iqdac_phase_update_wack, ctrl_rf2_iqdac_phase_update_wack, ctrl_rf1_iqdac_igain_arm_wack, ctrl_rf1_iqdac_qgain_arm_wack, ctrl_rf2_iqdac_igain_arm_wack, ctrl_rf2_iqdac_qgain_arm_wack, ctrl_rf1_iqdac_ctrl_wack, ctrl_rf2_iqdac_ctrl_wack, ctrl_iqdac_ram_addr_wack, ctrl_iqdac_ram_data_wack, ctrl_iqdac_ram_write_wack, ctrl_iqdac_ram_play_wack, ctrl_rf1_dds_ftw_valid_wack, ctrl_rf1_dds_ftw_wack, ctrl_rf2_dds_ftw_valid_wack, ctrl_rf2_dds_ftw_wack, ctrl_nco_reset_ctrl_wack) begin
init_hwinfo_echo_wreq <= (others => '0');
init_fw_update_we <= '0';
init_reconfigure_wreq <= '0';
......@@ -2532,10 +2644,14 @@ begin
ctrl_rf2_vtus_we <= '0';
ctrl_rf1_rfnco_we <= '0';
ctrl_rf2_rfnco_we <= '0';
ctrl_rf1_iqdac_igain_wreq <= '0';
ctrl_rf1_iqdac_qgain_wreq <= '0';
ctrl_rf2_iqdac_igain_wreq <= '0';
ctrl_rf2_iqdac_qgain_wreq <= '0';
ctrl_rf1_iqdac_phase_wreq <= '0';
ctrl_rf2_iqdac_phase_wreq <= '0';
ctrl_rf1_iqdac_phase_update_wreq <= '0';
ctrl_rf2_iqdac_phase_update_wreq <= '0';
ctrl_rf1_iqdac_igain_arm_wreq <= '0';
ctrl_rf1_iqdac_qgain_arm_wreq <= '0';
ctrl_rf2_iqdac_igain_arm_wreq <= '0';
ctrl_rf2_iqdac_qgain_arm_wreq <= '0';
ctrl_rf1_iqdac_ctrl_wreq <= '0';
ctrl_rf2_iqdac_ctrl_wreq <= '0';
ctrl_iqdac_ram_addr_wreq <= '0';
......@@ -3351,27 +3467,65 @@ begin
when "1" =>
case wr_adr_d0(11 downto 3) is
when "000000000" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg ctrl_rf1_iqdac_phase
ctrl_rf1_iqdac_phase_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf1_iqdac_phase_wack;
when "01" =>
-- Reg ctrl_rf2_iqdac_phase
ctrl_rf2_iqdac_phase_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf2_iqdac_phase_wack;
when "10" =>
-- Reg ctrl_rf1_iqdac_phase_update
ctrl_rf1_iqdac_phase_update_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf1_iqdac_phase_update_wack;
when "11" =>
-- Reg ctrl_rf2_iqdac_phase_update
ctrl_rf2_iqdac_phase_update_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf2_iqdac_phase_update_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "000000001" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg ctrl_rf1_iqdac_igain_arm
ctrl_rf1_iqdac_igain_arm_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf1_iqdac_igain_arm_wack;
when "01" =>
-- Reg ctrl_rf1_iqdac_qgain_arm
ctrl_rf1_iqdac_qgain_arm_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf1_iqdac_qgain_arm_wack;
when "10" =>
-- Reg ctrl_rf2_iqdac_igain_arm
ctrl_rf2_iqdac_igain_arm_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf2_iqdac_igain_arm_wack;
when "11" =>
-- Reg ctrl_rf2_iqdac_qgain_arm
ctrl_rf2_iqdac_qgain_arm_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf2_iqdac_qgain_arm_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "000000010" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg ctrl_rf1_iqdac_igain
ctrl_rf1_iqdac_igain_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf1_iqdac_igain_wack;
wr_ack_int <= wr_req_d0;
when "01" =>
-- Reg ctrl_rf1_iqdac_qgain
ctrl_rf1_iqdac_qgain_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf1_iqdac_qgain_wack;
wr_ack_int <= wr_req_d0;
when "10" =>
-- Reg ctrl_rf2_iqdac_igain
ctrl_rf2_iqdac_igain_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf2_iqdac_igain_wack;
wr_ack_int <= wr_req_d0;
when "11" =>
-- Reg ctrl_rf2_iqdac_qgain
ctrl_rf2_iqdac_qgain_wreq <= wr_req_d0;
wr_ack_int <= ctrl_rf2_iqdac_qgain_wack;
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "000000001" =>
when "000000011" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg ctrl_rf1_iqdac_ctrl
......@@ -3392,7 +3546,7 @@ begin
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "000000010" =>
when "000000100" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg ctrl_iqdac_ram_write
......@@ -3409,7 +3563,7 @@ begin
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "000000011" =>
when "000000101" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg ctrl_rf1_dds_ftw
......@@ -3430,7 +3584,7 @@ begin
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "000000100" =>
when "000000110" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg ctrl_rf2_dds_ftw_valid
......@@ -3439,7 +3593,7 @@ begin
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "000000101" =>
when "000000111" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg ctrl_rf2_dds_ftw
......@@ -3460,7 +3614,7 @@ begin
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "000000110" =>
when "000001000" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg ctrl_nco_reset_ctrl
......@@ -3481,7 +3635,7 @@ begin
end process;
-- Process for read requests.
process (adr_int, rd_req_int, init_hwinfo_serialNumber_i, init_hwinfo_ident_cardID_i, init_hwinfo_ident_extendedID_i, init_hwinfo_ident_jtagRemoteDisable_i, init_hwinfo_firmwareVersion_i, init_hwinfo_memMapVersion_i, init_hwinfo_echo_echo_reg, init_fw_update_i.dat, init_fw_update_rack, init_clock_ctrl_clk_sel_reg, init_clock_ctrl_mmcm_reset_reg, init_wrcore_ctrl_reset_n_reg, init_iodelay_ctrl_reset_reg, init_clock_status_mmcm_locked_i, init_clock_status_shift_busy_i, init_tmg_io_term_reg, init_tmg_io_oe_reg, init_tmg_clk_term_reg, init_tmg_clk_oe_reg, init_lemo_rf1_t1_start_sel_reg, init_lemo_rf1_t2_start_sel_reg, init_lemo_rf2_t1_start_sel_reg, init_lemo_rf2_t2_start_sel_reg, init_lemo_rf1_t1_stop_sel_reg, init_lemo_rf1_t2_stop_sel_reg, init_lemo_rf2_t1_stop_sel_reg, init_lemo_rf2_t2_stop_sel_reg, init_tmgio1_osel_reg, init_tmgio2_osel_reg, init_tmgio3_osel_reg, init_tmgio4_osel_reg, init_tmgclk1_osel_reg, init_tmgclk2_osel_reg, init_lemo_gpio_reg, init_lemo_ext_sel_reg, init_softstart_sel_reg, init_softstop_sel_reg, init_lemo_pulse_ext_reg, init_pin_ctrl_ext_10m_dir_reg, init_pin_ctrl_ext_pps_dir_reg, init_pll_status_error_i, init_pll_status_locked_i, init_pll_ctrl_sync_reg, init_dds_ctrl_reset_reg, init_dds_ctrl_profile_reg, init_dds_ioupdate_fdelay_reg, init_dds_ioupdate_odelay_reg, init_dds_status_sync_error_i, init_ocxo_ctrl_enable_reg, init_ocxo_uptime_val_i, init_nco_azimuthal_value_reg, init_nco_cabledelay_value_reg, init_nco_hb_value_reg, init_nco_h1_ftw_value_reg, init_nco_h1_prog_value_reg, init_nco_ctrl_reset_nco_reg, init_nco_ctrl_reset_slip_reg, init_nco_ctrl_reset_fsk_reg, init_nco_ctrl_rate_reg, init_nco_loc_or_wrs_params_sel_reg, init_svec_mup_ctrl_gpio_sel_reg, init_svec_mup_ctrl_led_sel_reg, init_svec_mup_ctrl_bclk_rfclk_sel_reg, init_svec_mup_ctrl_ila_sel_reg, init_svec_mup_rftrig_t1stop_reg, init_svec_mup_rftrig_t1start_reg, init_svec_mup_rftrig_t2stop_reg, init_svec_mup_rftrig_t2start_reg, init_svec_mup_fmc1_term_reg, init_svec_mup_fmc1_oe_n_reg, init_svec_mup_fmc1_led_reg, init_svec_mup_fmc2_term_reg, init_svec_mup_fmc2_oe_n_reg, init_svec_mup_fmc2_led_reg, init_wrs_rxframe_ftw_value_i, init_wrs_rxframe_ctrl_i, init_wrs_rxframe_counter_i, init_wrs_rxframe_rxwrtimestamp_i, init_wrs_rxframe_txwrtimestamp_i, init_wrs_rxframe_rftimestamp_i, init_wrc_tai_value_i, init_wrc_cycles_value_i, init_wrc_status_linkup_i, init_wrc_status_time_valid_i, init_wrc_page0_reg, init_wrc_page1_reg, init_txframe_ftw_h1_main_reg, init_txframe_ftw_h1_prog_reg, init_txframe_ftw_h1_on_reg, init_txframe_dftw_h1_slip1_reg, init_txframe_dftw_h1_slip2_reg, init_txframe_setpoint1_reg, init_txframe_setpoint2_reg, init_txframe_setpoint3_reg, init_txframe_setpoint4_reg, init_txframe_setpoint5_reg, init_txframe_setpoint6_reg, init_txframe_setpoint7_reg, init_txframe_setpoint8_reg, init_txframe_noise_reg, init_txframe_control_reg, init_pll_spi_i.dat, init_pll_spi_rack, init_rf_spi_i.dat, init_rf_spi_rack, init_rf_i.dat, init_rf_rack, init_framerxtx_i.dat, init_framerxtx_rack, init_wrpc_i.dat, init_wrpc_rack, ctrl_rf1_vtus_i.dat, ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack, ctrl_rf1_rfnco_i.dat, ctrl_rf1_rfnco_rack, ctrl_rf2_rfnco_i.dat, ctrl_rf2_rfnco_rack, ctrl_rf1_iqdac_igain_reg, ctrl_rf1_iqdac_qgain_reg, ctrl_rf2_iqdac_igain_reg, ctrl_rf2_iqdac_qgain_reg, ctrl_rf1_iqdac_ctrl_reg, ctrl_rf2_iqdac_ctrl_reg, ctrl_iqdac_ram_addr_reg, ctrl_iqdac_ram_data_reg, ctrl_iqdac_ram_write_reg, ctrl_iqdac_ram_play_reg, ctrl_rf1_dds_ftw_valid_reg, ctrl_rf1_dds_ftw_reg, ctrl_rf2_dds_ftw_valid_reg, ctrl_rf2_dds_ftw_reg, ctrl_nco_reset_ctrl_mask_dds_reg, ctrl_nco_reset_ctrl_mask_rfnco_ch1_reg, ctrl_nco_reset_ctrl_mask_rfnco_ch2_reg, ctrl_nco_reset_ctrl_mask_rf1_trig1_reg, ctrl_nco_reset_ctrl_mask_rf2_trig1_reg) begin
process (adr_int, rd_req_int, init_hwinfo_serialNumber_i, init_hwinfo_ident_cardID_i, init_hwinfo_ident_extendedID_i, init_hwinfo_ident_jtagRemoteDisable_i, init_hwinfo_firmwareVersion_i, init_hwinfo_memMapVersion_i, init_hwinfo_echo_echo_reg, init_fw_update_i.dat, init_fw_update_rack, init_clock_ctrl_clk_sel_reg, init_clock_ctrl_mmcm_reset_reg, init_wrcore_ctrl_reset_n_reg, init_iodelay_ctrl_reset_reg, init_clock_status_mmcm_locked_i, init_clock_status_shift_busy_i, init_tmg_io_term_reg, init_tmg_io_oe_reg, init_tmg_clk_term_reg, init_tmg_clk_oe_reg, init_lemo_rf1_t1_start_sel_reg, init_lemo_rf1_t2_start_sel_reg, init_lemo_rf2_t1_start_sel_reg, init_lemo_rf2_t2_start_sel_reg, init_lemo_rf1_t1_stop_sel_reg, init_lemo_rf1_t2_stop_sel_reg, init_lemo_rf2_t1_stop_sel_reg, init_lemo_rf2_t2_stop_sel_reg, init_tmgio1_osel_reg, init_tmgio2_osel_reg, init_tmgio3_osel_reg, init_tmgio4_osel_reg, init_tmgclk1_osel_reg, init_tmgclk2_osel_reg, init_lemo_gpio_reg, init_lemo_ext_sel_reg, init_softstart_sel_reg, init_softstop_sel_reg, init_lemo_pulse_ext_reg, init_pin_ctrl_ext_10m_dir_reg, init_pin_ctrl_ext_pps_dir_reg, init_pll_status_error_i, init_pll_status_locked_i, init_pll_ctrl_sync_reg, init_dds_ctrl_reset_reg, init_dds_ctrl_profile_reg, init_dds_ioupdate_fdelay_reg, init_dds_ioupdate_odelay_reg, init_dds_status_sync_error_i, init_ocxo_ctrl_enable_reg, init_ocxo_uptime_val_i, init_nco_azimuthal_value_reg, init_nco_cabledelay_value_reg, init_nco_hb_value_reg, init_nco_h1_ftw_value_reg, init_nco_h1_prog_value_reg, init_nco_ctrl_reset_nco_reg, init_nco_ctrl_reset_slip_reg, init_nco_ctrl_reset_fsk_reg, init_nco_ctrl_rate_reg, init_nco_loc_or_wrs_params_sel_reg, init_svec_mup_ctrl_gpio_sel_reg, init_svec_mup_ctrl_led_sel_reg, init_svec_mup_ctrl_bclk_rfclk_sel_reg, init_svec_mup_ctrl_ila_sel_reg, init_svec_mup_rftrig_t1stop_reg, init_svec_mup_rftrig_t1start_reg, init_svec_mup_rftrig_t2stop_reg, init_svec_mup_rftrig_t2start_reg, init_svec_mup_fmc1_term_reg, init_svec_mup_fmc1_oe_n_reg, init_svec_mup_fmc1_led_reg, init_svec_mup_fmc2_term_reg, init_svec_mup_fmc2_oe_n_reg, init_svec_mup_fmc2_led_reg, init_wrs_rxframe_ftw_value_i, init_wrs_rxframe_ctrl_i, init_wrs_rxframe_counter_i, init_wrs_rxframe_rxwrtimestamp_i, init_wrs_rxframe_txwrtimestamp_i, init_wrs_rxframe_rftimestamp_i, init_wrc_tai_value_i, init_wrc_cycles_value_i, init_wrc_status_linkup_i, init_wrc_status_time_valid_i, init_wrc_page0_reg, init_wrc_page1_reg, init_txframe_ftw_h1_main_reg, init_txframe_ftw_h1_prog_reg, init_txframe_ftw_h1_on_reg, init_txframe_dftw_h1_slip1_reg, init_txframe_dftw_h1_slip2_reg, init_txframe_setpoint1_reg, init_txframe_setpoint2_reg, init_txframe_setpoint3_reg, init_txframe_setpoint4_reg, init_txframe_setpoint5_reg, init_txframe_setpoint6_reg, init_txframe_setpoint7_reg, init_txframe_setpoint8_reg, init_txframe_noise_reg, init_txframe_control_reg, init_pll_spi_i.dat, init_pll_spi_rack, init_rf_spi_i.dat, init_rf_spi_rack, init_rf_i.dat, init_rf_rack, init_framerxtx_i.dat, init_framerxtx_rack, init_wrpc_i.dat, init_wrpc_rack, ctrl_rf1_vtus_i.dat, ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack, ctrl_rf1_rfnco_i.dat, ctrl_rf1_rfnco_rack, ctrl_rf2_rfnco_i.dat, ctrl_rf2_rfnco_rack, ctrl_rf1_iqdac_phase_reg, ctrl_rf2_iqdac_phase_reg, ctrl_rf1_iqdac_igain_arm_reg, ctrl_rf1_iqdac_qgain_arm_reg, ctrl_rf2_iqdac_igain_arm_reg, ctrl_rf2_iqdac_qgain_arm_reg, ctrl_rf1_iqdac_igain_i, ctrl_rf1_iqdac_qgain_i, ctrl_rf2_iqdac_igain_i, ctrl_rf2_iqdac_qgain_i, ctrl_rf1_iqdac_ctrl_reg, ctrl_rf2_iqdac_ctrl_reg, ctrl_iqdac_ram_addr_reg, ctrl_iqdac_ram_data_reg, ctrl_iqdac_ram_write_reg, ctrl_iqdac_ram_play_reg, ctrl_rf1_dds_ftw_valid_reg, ctrl_rf1_dds_ftw_reg, ctrl_rf2_dds_ftw_valid_reg, ctrl_rf2_dds_ftw_reg, ctrl_nco_reset_ctrl_mask_dds_reg, ctrl_nco_reset_ctrl_mask_rfnco_ch1_reg, ctrl_nco_reset_ctrl_mask_rfnco_ch2_reg, ctrl_nco_reset_ctrl_mask_rf1_trig1_reg, ctrl_nco_reset_ctrl_mask_rf2_trig1_reg) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
init_fw_update_re <= '0';
......@@ -4428,27 +4582,71 @@ begin
when "1" =>
case adr_int(11 downto 3) is
when "000000000" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg ctrl_rf1_iqdac_phase
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= ctrl_rf1_iqdac_phase_reg;
when "01" =>
-- Reg ctrl_rf2_iqdac_phase
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= ctrl_rf2_iqdac_phase_reg;
when "10" =>
-- Reg ctrl_rf1_iqdac_phase_update
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= '0';
rd_dat_d0(15 downto 1) <= (others => '0');
when "11" =>
-- Reg ctrl_rf2_iqdac_phase_update
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= '0';
rd_dat_d0(15 downto 1) <= (others => '0');
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "000000001" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg ctrl_rf1_iqdac_igain_arm
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= ctrl_rf1_iqdac_igain_arm_reg;
when "01" =>
-- Reg ctrl_rf1_iqdac_qgain_arm
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= ctrl_rf1_iqdac_qgain_arm_reg;
when "10" =>
-- Reg ctrl_rf2_iqdac_igain_arm
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= ctrl_rf2_iqdac_igain_arm_reg;
when "11" =>
-- Reg ctrl_rf2_iqdac_qgain_arm
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= ctrl_rf2_iqdac_qgain_arm_reg;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "000000010" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg ctrl_rf1_iqdac_igain
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= ctrl_rf1_iqdac_igain_reg;
rd_dat_d0 <= ctrl_rf1_iqdac_igain_i;
when "01" =>
-- Reg ctrl_rf1_iqdac_qgain
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= ctrl_rf1_iqdac_qgain_reg;
rd_dat_d0 <= ctrl_rf1_iqdac_qgain_i;
when "10" =>
-- Reg ctrl_rf2_iqdac_igain
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= ctrl_rf2_iqdac_igain_reg;
rd_dat_d0 <= ctrl_rf2_iqdac_igain_i;
when "11" =>
-- Reg ctrl_rf2_iqdac_qgain
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= ctrl_rf2_iqdac_qgain_reg;
rd_dat_d0 <= ctrl_rf2_iqdac_qgain_i;
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "000000001" =>
when "000000011" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg ctrl_rf1_iqdac_ctrl
......@@ -4469,7 +4667,7 @@ begin
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "000000010" =>
when "000000100" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg ctrl_iqdac_ram_write
......@@ -4486,7 +4684,7 @@ begin
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "000000011" =>
when "000000101" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg ctrl_rf1_dds_ftw
......@@ -4507,7 +4705,7 @@ begin
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "000000100" =>
when "000000110" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg ctrl_rf2_dds_ftw_valid
......@@ -4516,7 +4714,7 @@ begin
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "000000101" =>
when "000000111" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg ctrl_rf2_dds_ftw
......@@ -4537,7 +4735,7 @@ begin
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "000000110" =>
when "000001000" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg ctrl_nco_reset_ctrl
......
software/include/wr2rf_ctrl_regs.h
View file @ 08d1bc0b
......@@ -2,7 +2,7 @@
#define __CHEBY__WR2RF_CTRL_REGS__H__
#include "wr2rf_rftrigger_regs.h"
#define WR2RF_CTRL_REGS_SIZE 12338 /* 0x3032 */
#define WR2RF_CTRL_REGS_SIZE 12354 /* 0x3042 */
/* Registers for rf1 vtus */
#define WR2RF_CTRL_REGS_RF1_VTUS 0x0UL
......@@ -20,50 +20,76 @@
#define WR2RF_CTRL_REGS_RF2_RFNCO 0x2000UL
#define WR2RF_CTRL_REGS_RF2_RFNCO_SIZE 4096 /* 0x1000 = 4KB */
/* phase represented as a signed integer */
#define WR2RF_CTRL_REGS_RF1_IQDAC_PHASE 0x3000UL
/* phase represented as a signed integer */
#define WR2RF_CTRL_REGS_RF2_IQDAC_PHASE 0x3002UL
/* phase represented as a signed integer */
#define WR2RF_CTRL_REGS_RF1_IQDAC_PHASE_UPDATE 0x3004UL
#define WR2RF_CTRL_REGS_RF1_IQDAC_PHASE_UPDATE_VALID 0x1UL
/* phase represented as a signed integer */
#define WR2RF_CTRL_REGS_RF2_IQDAC_PHASE_UPDATE 0x3006UL
#define WR2RF_CTRL_REGS_RF2_IQDAC_PHASE_UPDATE_VALID 0x1UL
/* I ampl/phase for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF1_IQDAC_IGAIN_ARM 0x3008UL
/* Q ampl/phase for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF1_IQDAC_QGAIN_ARM 0x300aUL
/* I ampl/phase for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF2_IQDAC_IGAIN_ARM 0x300cUL
/* Q ampl/phase for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF2_IQDAC_QGAIN_ARM 0x300eUL
/* I gain for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF1_IQDAC_IGAIN 0x3000UL
#define WR2RF_CTRL_REGS_RF1_IQDAC_IGAIN 0x3010UL
/* I gain for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF1_IQDAC_QGAIN 0x3002UL
#define WR2RF_CTRL_REGS_RF1_IQDAC_QGAIN 0x3012UL
/* I gain for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF2_IQDAC_IGAIN 0x3004UL
#define WR2RF_CTRL_REGS_RF2_IQDAC_IGAIN 0x3014UL
/* I gain for IQ complex multiplier */
#define WR2RF_CTRL_REGS_RF2_IQDAC_QGAIN 0x3006UL
#define WR2RF_CTRL_REGS_RF2_IQDAC_QGAIN 0x3016UL
/* Select iqdac I + Q sources */
#define WR2RF_CTRL_REGS_RF1_IQDAC_CTRL 0x3008UL
#define WR2RF_CTRL_REGS_RF1_IQDAC_CTRL 0x3018UL
/* Select iqdac I + Q sources */
#define WR2RF_CTRL_REGS_RF2_IQDAC_CTRL 0x300aUL
#define WR2RF_CTRL_REGS_RF2_IQDAC_CTRL 0x301aUL
/* Select iqdac ram address */
#define WR2RF_CTRL_REGS_IQDAC_RAM_ADDR 0x300cUL
#define WR2RF_CTRL_REGS_IQDAC_RAM_ADDR 0x301cUL
/* iqdac ram data to be written at address iqdac_ram_addr */
#define WR2RF_CTRL_REGS_IQDAC_RAM_DATA 0x300eUL
#define WR2RF_CTRL_REGS_IQDAC_RAM_DATA 0x301eUL
/* Some magic controls bit tbd */
#define WR2RF_CTRL_REGS_IQDAC_RAM_WRITE 0x3010UL
#define WR2RF_CTRL_REGS_IQDAC_RAM_WRITE 0x3020UL
/* Some magic controls bit tbd */
#define WR2RF_CTRL_REGS_IQDAC_RAM_PLAY 0x3012UL
#define WR2RF_CTRL_REGS_IQDAC_RAM_PLAY 0x3022UL
/* None */
#define WR2RF_CTRL_REGS_RF1_DDS_FTW_VALID 0x3014UL
#define WR2RF_CTRL_REGS_RF1_DDS_FTW_VALID 0x3024UL
/* Phase increment value to xilinx dds core */
#define WR2RF_CTRL_REGS_RF1_DDS_FTW 0x3018UL
#define WR2RF_CTRL_REGS_RF1_DDS_FTW 0x3028UL
/* None */
#define WR2RF_CTRL_REGS_RF2_DDS_FTW_VALID 0x3020UL
#define WR2RF_CTRL_REGS_RF2_DDS_FTW_VALID 0x3030UL
/* Phase increment value to xilinx dds core */
#define WR2RF_CTRL_REGS_RF2_DDS_FTW 0x3028UL
#define WR2RF_CTRL_REGS_RF2_DDS_FTW 0x3038UL
/* Configures behaviour for how an nco_reset will operate */
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL 0x3030UL
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL 0x3040UL
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_DDS 0x1UL
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_RFNCO_CH1 0x2UL
#define WR2RF_CTRL_REGS_NCO_RESET_CTRL_MASK_RFNCO_CH2 0x4UL
......@@ -90,55 +116,79 @@ struct wr2rf_ctrl_regs {
/* [0x2000]: SUBMAP Registers for rf2 rfnco */
uint32_t rf2_rfnco[1024];
/* [0x3000]: REG (rw) I gain for IQ complex multiplier */
/* [0x3000]: REG (rw) phase represented as a signed integer */
uint16_t rf1_iqdac_phase;
/* [0x3002]: REG (rw) phase represented as a signed integer */
uint16_t rf2_iqdac_phase;
/* [0x3004]: REG (rw) phase represented as a signed integer */
uint16_t rf1_iqdac_phase_update;
/* [0x3006]: REG (rw) phase represented as a signed integer */
uint16_t rf2_iqdac_phase_update;
/* [0x3008]: REG (rw) I ampl/phase for IQ complex multiplier */
uint16_t rf1_iqdac_igain_arm;
/* [0x300a]: REG (rw) Q ampl/phase for IQ complex multiplier */
uint16_t rf1_iqdac_qgain_arm;
/* [0x300c]: REG (rw) I ampl/phase for IQ complex multiplier */
uint16_t rf2_iqdac_igain_arm;
/* [0x300e]: REG (rw) Q ampl/phase for IQ complex multiplier */
uint16_t rf2_iqdac_qgain_arm;
/* [0x3010]: REG (ro) I gain for IQ complex multiplier */
uint16_t rf1_iqdac_igain;
/* [0x3002]: REG (rw) I gain for IQ complex multiplier */
/* [0x3012]: REG (ro) I gain for IQ complex multiplier */
uint16_t rf1_iqdac_qgain;
/* [0x3004]: REG (rw) I gain for IQ complex multiplier */
/* [0x3014]: REG (ro) I gain for IQ complex multiplier */
uint16_t rf2_iqdac_igain;
/* [0x3006]: REG (rw) I gain for IQ complex multiplier */
/* [0x3016]: REG (ro) I gain for IQ complex multiplier */
uint16_t rf2_iqdac_qgain;
/* [0x3008]: REG (rw) Select iqdac I + Q sources */
/* [0x3018]: REG (rw) Select iqdac I + Q sources */
uint16_t rf1_iqdac_ctrl;
/* [0x300a]: REG (rw) Select iqdac I + Q sources */
/* [0x301a]: REG (rw) Select iqdac I + Q sources */
uint16_t rf2_iqdac_ctrl;
/* [0x300c]: REG (rw) Select iqdac ram address */
/* [0x301c]: REG (rw) Select iqdac ram address */
uint16_t iqdac_ram_addr;
/* [0x300e]: REG (rw) iqdac ram data to be written at address iqdac_ram_addr */
/* [0x301e]: REG (rw) iqdac ram data to be written at address iqdac_ram_addr */
uint16_t iqdac_ram_data;
/* [0x3010]: REG (rw) Some magic controls bit tbd */
/* [0x3020]: REG (rw) Some magic controls bit tbd */
uint16_t iqdac_ram_write;
/* [0x3012]: REG (rw) Some magic controls bit tbd */
/* [0x3022]: REG (rw) Some magic controls bit tbd */
uint16_t iqdac_ram_play;
/* [0x3014]: REG (rw) (no description) */
/* [0x3024]: REG (rw) (no description) */
uint16_t rf1_dds_ftw_valid;
/* padding to: 12312 words */
/* padding to: 12328 words */
uint8_t __padding_2[2];
/* [0x3018]: REG (rw) Phase increment value to xilinx dds core */
/* [0x3028]: REG (rw) Phase increment value to xilinx dds core */
uint64_t rf1_dds_ftw;
/* [0x3020]: REG (rw) (no description) */
/* [0x3030]: REG (rw) (no description) */
uint16_t rf2_dds_ftw_valid;
/* padding to: 12328 words */
/* padding to: 12344 words */
uint8_t __padding_3[6];
/* [0x3028]: REG (rw) Phase increment value to xilinx dds core */
/* [0x3038]: REG (rw) Phase increment value to xilinx dds core */
uint64_t rf2_dds_ftw;
/* [0x3030]: REG (rw) Configures behaviour for how an nco_reset will operate */
/* [0x3040]: REG (rw) Configures behaviour for how an nco_reset will operate */
uint16_t nco_reset_ctrl;
};
......
software/include/wr2rf_init_regs.h
View file @ 08d1bc0b
......@@ -2,8 +2,8 @@
#define __CHEBY__WR2RF_INIT_REGS__H__
#include "oc_spi16_regs.h"
#include "hwInfo.h"
#include "wr2rf_init_rf_regs.h"
#include "hwInfo.h"
#define WR2RF_INIT_REGS_SIZE 16384 /* 0x4000 = 16KB */
/* RF indentification */
......
software/include/wr2rf_rftrigger_regs.h
View file @ 08d1bc0b
#ifndef __CHEBY__WR2RF_RFTRIGGER_REGS__H__
#define __CHEBY__WR2RF_RFTRIGGER_REGS__H__
#include "vtudiag_regs.h"
#include "trigunit_regs.h"
#include "vtudiag_regs.h"
#define WR2RF_RFTRIGGER_REGS_SIZE 272 /* 0x110 */
/* None */
......
software/include/wr2rf_vme_regs.h
View file @ 08d1bc0b
......@@ -21,7 +21,7 @@ struct wr2rf_vme_regs {
struct wr2rf_ctrl_regs ctrl;
/* padding to: 16384 words */
uint8_t __padding_0[4046];
uint8_t __padding_0[4030];
};
#endif /* __CHEBY__WR2RF_VME_REGS__H__ */
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