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The picture below depicts the connections between the DDS and FPGA that are important to
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consider for timing calibration.
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![DDS-IOUpdate](uploads/230be8107899fe592e0b1386436be343/Screenshot_from_2023-09-12_08-56-08.png)
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The signal IOUpdate resets the phase accumulators on the DDS AD9910. Internally, this signal is
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sampled by a clock called SYNC_CLK which is divided by 4 version of the SYS_CLK frequency.
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The SYS_CLK is derived from the incoming 1 GHz reference clock from the PLL. We have to
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... | ... | @@ -52,6 +54,8 @@ be avoided. The following functional overview highlights the different clock dom |
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interfaces. Blue, denotes a WR clock domain, red denotes RF clocks and signals and orange/yellow
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indicate the VTU clock, a divided (by 8) version of the RF clock.
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![VTU-nco-reset](uploads/4192e6e1020a383adf2bd595e1026013/Screenshot_from_2023-09-12_08-58-12.png)
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Where can metastability be introduced into the system?
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* The phase of the RFNCO is reset within the WR clock domain. This signal must be
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