... | ... | @@ -162,7 +162,7 @@ delay on the trigger unit output from the FPGA has two elements: |
|
|
|
|
|
* An ODELAY cell that provides changes in delay of 78 ps, up to 31 x 78 ps
|
|
|
|
|
|
* A half-cycle delay
|
|
|
* A half-cycle delay (RF clock cycle)
|
|
|
|
|
|
Combined together, the half-cycle delay and ODELAY should provide close to 5 ns of total delay, if
|
|
|
the incoming RF clock has a 200 MHz frequency.
|
... | ... | @@ -178,7 +178,7 @@ something like this for trigger unit 1 on RF channel 1: |
|
|
./wr2rf -s $slot vtu-odelay 1.1 1 0x10
|
|
|
```
|
|
|
|
|
|
and so on, depending on where the RF sampling point changes.
|
|
|
and so on, depending on where the RF sampling point changes. The value to be set is just the inverted half-cycle and same odelay.
|
|
|
|
|
|
There is a small chance that the metastability region cannot be found. In this event, set the delay to midpoint of the search, e.g.
|
|
|
```
|
... | ... | |