... | ... | @@ -13,11 +13,20 @@ If the ad9910 **is** outputting a stable signal, when the nco_reset signal is as |
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![ad9910_warm_start](uploads/cf1f9f772a1414d88ce73877ad38e87f/ad9910_warm_start.png)
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## RFNCO versus Xilinx DDS, glitchy RF close 1 usec **after** nco_reset
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## RFNCO versus Xilinx DDS, glitchy RF close to 1 usec **after** nco_reset
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In the following plot, I'm mixing the IQDAC and AD9910 DDS. On RF1 channel 1 (blue) I send a signal from a Xilinx DDS, whilst on channel 2 (green) I show the mixed output when deriving the IF via the RFNCO and IQModulation blocks.
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The nco_reset (yellow) is the triggering cause for this plot. When using the RFNCO and IQModulation blocks there is a glitch close to 950 ns after nco_reset. This glitch in the RF is **not** present if I use the output from a Xilinx DDS.
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We have to delay the trigger unit sync signal until we have stable RF, otherwise our trigger unit output will be glitchy too. For tracking the RF during a ramp we'd like this delay to be as small as possible but guaranteeing stable/reproducible RF.
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![RF_versus_RFNCO_and_XilinxDDS](uploads/32fad08bcd0948b5006b234326b48018/RF_versus_RFNCO_and_XilinxDDS.png) |
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![RF_versus_RFNCO_and_XilinxDDS](uploads/32fad08bcd0948b5006b234326b48018/RF_versus_RFNCO_and_XilinxDDS.png)
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UPDATE: After simulating the RFNCO and IQModulation blocks it takes 744 ns for the IF signal to be generated within the FPGA. This breaks down as:
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* 600 ns or 75 cycles latency for the RFNCO
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* 144 ns or 18 cycles latency for the IQModulation block
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Then there are a few register stages to get off the FPGA, IQDAC, Mixer + RF analog components (amplifiers and attenuators) plus RF switches and finally 8 ns coax cable, probably account for the 200 ns increase to ~950 ns.
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Therefore we observe two glitches in the output RF:
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* the first at around 120 ns is due to ad9910 re-syncing
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* the second at around 950 ns is due to the IF RF signal re-syncing |
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