FPGA reports wrong values in ns counter register
During the synchronization the register that holds the ns counter/16 happens to be greater than 1000000000/16. As an effect during synchronization process when logs in ppsi are enabled, in some logs the fractional part of a second in logs is negative:
2021-08-21T05:43:44.183104+00:00 wrch1 ppsi: diag-fsm-1-wri1-1-wr-raw: 1629524656.-186: uncalibrated: reenter in 624 ms
It is not known yet if this problem has any side effects on synchronization or software.
The mentioned register is at the address:
0x10010000 + 0x500 + 1
Problem seen on a slave during automatic testing when the master was rebooted several times. Master has the same time set at every boot. The NTP was enabled so there were jumps back in time on slave.
The same problem was observed in WRPC