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White Rabbit Switch - Software
Commit bf0073bb authored by li hongming's avatar li hongming
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Support aligning the PPS out to PPS input when WRSFL works as GM. 

    1. Add new paramter CONFIG_EXT_PPS_LATENCY_PS in dot-config. Calib-
ration is needed to align the PPS out to PPS input in GM mode.
    2. Add new variable ext_pps_latency_ps in struct spll_stats, using it
to transfer the ext_pps_latency parameter to WRPC-SW.
    3. Change SPLL_STATS_VER to 4, modify the related function.
    4. Add a new tool function: wrs_ext_pps_latency, which will change
the Main PLL phase shift in GM mode, according to the parameter
CONFIG_EXT_PPS_LATENCY_PS in dot-config. Add this new function to startup-
mb.sh, making it autostart.
parent 7f667342
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Showing with 117 additions and 6 deletions
Kconfig
View file @ bf0073bb
......@@ -857,6 +857,19 @@ config WRSAUXCLK_PPSHIFT
should be re-calibrated. Otherwise, 1-PPS output will be shifted
from the WR timescale by <steps>*150ps.
config EXT_PPS_LATENCY_PS
string "Compensate signal skew between PPS IN and PPS OUT"
default "13980"
help
--extppslatency parameter of wrs_ext_pps_lantency
If one needs to precisely align 1-PPS output with 1-PPS input when WRS
works as GrandMaster, calibration are needed to overcome the signal
skew between the 1-PPS input and 10MHz clock input. As the component
variance of different clock source and WRS, this lantency parameter
should be calibrated one by one to achieve PPS alignment with high
accuracy.
endmenu
menu "NIC throttling configuration"
......
configs/wrs_release_defconfig
View file @ bf0073bb
......@@ -116,6 +116,7 @@ CONFIG_WRSAUXCLK_DUTY="0.5"
CONFIG_WRSAUXCLK_CSHIFT="36"
CONFIG_WRSAUXCLK_SIGDEL="9"
CONFIG_WRSAUXCLK_PPSHIFT="0"
CONFIG_EXT_PPS_LATENCY_PS="13980"
#
# NIC throttling configuration
......
doc/wrs-user-manual.in
View file @ bf0073bb
......@@ -891,9 +891,11 @@ appropriate way, before the respective service is started.
@itemx CONFIG_WRSAUXCLK_CSHIFT
@itemx CONFIG_WRSAUXCLK_SIGDEL
@itemx CONFIG_WRSAUXCLK_PPSHIFT
@itemx CONFIG_EXT_PPS_LATENCY_PS
Set of parameters passed to @t{wrs_auxclk} at boot time to generate
WR-synchronized 10MHz clock on the @i{clk2} output.
WR-synchronized 10MHz clock on the @i{clk2} output, as well as aligning
the 1-PPS input and 1-PPS output.
For more information please check @ref{wrs_auxclk}.
@item CONFIG_NIC_THROTTLING_ENABLED
......
userspace/libwr/include/libwr/softpll_export.h
View file @ bf0073bb
......@@ -57,7 +57,7 @@
#define ALIGN_STATE_WAIT_CLKIN 9
#define ALIGN_STATE_WAIT_PLOCK 10
#define SPLL_STATS_VER 2
#define SPLL_STATS_VER 4
/* info reported through .stat section */
/* due to endiannes problem strings has to be 4 bytes alligned */
......@@ -78,6 +78,8 @@ struct spll_stats {
char build_date[16];
char build_time[16];
char build_by[32];
int ext_pps_latency_ps; // added by hm
};
extern struct spll_stats stats;
......
userspace/rootfs_override/etc/init.d/wrs_auxclk.sh
View file @ bf0073bb
......@@ -56,6 +56,7 @@ fi
echo -n "Configuring external clock clk2: "
eval /wr/bin/wrs_auxclk $p_freq $p_duty $p_cshift $p_sigdel $p_ppshift $LOGPIPE
ret=$?
if [ $ret -eq 0 ]; then
echo "OK"
echo "ok" > $wrs_auxclk_set_status_file
......
userspace/rootfs_override/var/www/data/wrs-data.php
View file @ bf0073bb
......@@ -278,6 +278,12 @@ $WRS_FORMS = Array(
'value' => $_SESSION["KCONFIG"]["CONFIG_WRSAUXCLK_PPSHIFT"],
'vname' => "auxclkppshift",
),
'CONFIG_WRSAUXCLK_05' => Array(
'key' => "CONFIG_EXT_PPS_LATENCY_PS",
'name' => "EXT PPS LATENCY",
'value' => $_SESSION["KCONFIG"]["CONFIG_EXT_PPS_LATENCY_PS"],
'vname' => "extppslatency",
),
),
);
......
userspace/rootfs_override/wr/sbin/startup-mb.sh
View file @ bf0073bb
#!/bin/ash
export WR_HOME="/wr"
dotconfig=/wr/etc/dot-config
if [ -f $dotconfig ]; then
. $dotconfig
else
# exit
echo "dot-config not found! Don't setup wrs_auxclk"
exit 1
fi
insmod $WR_HOME/lib/modules/asix.ko
echo "Using DHCP to get IP for eth1"
udhcpc -b -i eth1
......@@ -94,6 +104,10 @@ else
exit
fi
if [ ! -z "$CONFIG_EXT_PPS_LATENCY_PS" ]; then
ext_pps_latency="-l "$CONFIG_EXT_PPS_LATENCY_PS;
fi
/wr/bin/wrs_ext_pps_latency $ext_pps_latency
insmod $WR_HOME/lib/modules/htvic.ko
insmod $WR_HOME/lib/modules/wrs_devices.ko
......
userspace/snmpd/wrsSpllStatusGroup.c
View file @ bf0073bb
......@@ -49,8 +49,7 @@ time_t wrsSpllStatus_data_fill(void)
return time_update;
}
/* check version of SPLL's stat structure, versions 1 and 2 are ok */
// if ((spll_stats_p->ver == 1) || (spll_stats_p->ver == 2)) {
if (spll_stats_p->ver <= 3 ) {
if (spll_stats_p->ver <= 4 ) {
wrsSpllStatus_s.wrsSpllMode = spll_stats_p->mode;
wrsSpllStatus_s.wrsSpllIrqCnt = spll_stats_p->irq_cnt;
wrsSpllStatus_s.wrsSpllSeqState = spll_stats_p->seq_state;
......@@ -61,6 +60,7 @@ time_t wrsSpllStatus_data_fill(void)
wrsSpllStatus_s.wrsSpllMY = spll_stats_p->M_y;
wrsSpllStatus_s.wrsSpllDelCnt = spll_stats_p->del_cnt;
}
/* there was an update, return current time */
return time_update;
}
......
userspace/snmpd/wrsSpllVersionGroup.c
View file @ bf0073bb
......@@ -44,7 +44,7 @@ time_t wrsSpllVersion_data_fill(void)
}
/* check version of SPLL's stat structure, version fields are from
* version 2 */
if (spll_stats_p->ver == 2 || spll_stats_p->ver == 3) {
if (spll_stats_p->ver <= 4) {
int len;
strncpy_e(wrsSpllVersion_s.wrsSpllVersion, spll_stats_p->commit_id, 32);
/* concatenate date and time */
......@@ -55,9 +55,10 @@ time_t wrsSpllVersion_data_fill(void)
strncpy_e(&wrsSpllVersion_s.wrsSpllBuildDate[len + 1], spll_stats_p->build_time, 16 - 1);
}
/* buil_by was introduced in version 3 */
if (spll_stats_p->ver == 3) {
if (spll_stats_p->ver >= 3) {
strncpy_e(wrsSpllVersion_s.wrsSpllBuildBy, spll_stats_p->build_by, 32);
}
/* there was an update, return current time */
return time_update;
}
......
userspace/tools/.gitignore
View file @ bf0073bb
......@@ -19,6 +19,7 @@ wrs_dump_shmem
sdb-read
nbtee
wrs_auxclk
wrs_ext_pps_latency
wrs_checkcfg
mkpasswd
wrs_status_led
......
userspace/tools/Makefile
View file @ bf0073bb
......@@ -5,6 +5,7 @@ TOOLS += wrs_vlans wrs_dump_shmem
TOOLS += sdb-read
TOOLS += nbtee
TOOLS += wrs_auxclk
TOOLS += wrs_ext_pps_latency
TOOLS += wrs_checkcfg
TOOLS += wrs_status_led
TOOLS += mkpasswd
......
userspace/tools/wrs_dump_shmem.c
View file @ bf0073bb
......@@ -804,6 +804,7 @@ struct dump_info spll_stats_info[] = {
DUMP_FIELD_SIZE(char_e, build_date, 16),
DUMP_FIELD_SIZE(char_e, build_time, 16),
DUMP_FIELD_SIZE(char_e, build_by, 32),
DUMP_FIELD(int, ext_pps_latency_ps),
};
static int dump_spll_mem(struct spll_stats *spll)
......
userspace/tools/wrs_ext_pps_latency.c 0 → 100644
View file @ bf0073bb
#include <stdio.h>
#include <getopt.h>
#include <unistd.h>
#include <stdlib.h>
#include <stddef.h>
#include <libwr/switch_hw.h>
#include "fpga_io.h"
#include <libwr/softpll.h>
#include <libwr/util.h>
/*******************/
int print_help(char *prgname)
{
fprintf(stderr, "Use: %s [-l <ps>]"
" \n", prgname);
return 0;
}
int set_ext_pps_latency(char *prgname, int latency)
{
static struct spll_stats *spll_stats_p;
spll_stats_p = create_map(FPGA_SPLL_STAT,
sizeof(*spll_stats_p));
if (!spll_stats_p){
fprintf(stderr, "%s: unable to mmap\n", prgname);
return 1;
}
/* check magic number in SPLL stat memory */
if (spll_stats_p->magic != SPLL_MAGIC) {
/* wrong magic */
fprintf(stderr, "%s: Wrong SPLL magic number\n", prgname);
return 1;
}
if (spll_stats_p->ver >= 4 ) {
fprintf(stderr, "%s: Set external PPS latency to %d ps\n", prgname, latency);
spll_stats_p->ext_pps_latency_ps = latency;
}
return 0;
}
int main(int argc, char *argv[])
{
char *prgname = argv[0];
int c;
int ret;
while ((c = getopt(argc, argv, "hl:")) != -1) {
switch (c) {
case 'h':
print_help(prgname);
ret = 1;
break;
case 'l':
ret= set_ext_pps_latency(prgname, atoi(optarg));
break;
default:
print_help(prgname);
exit(1);
}
}
return ret;
}
\ No newline at end of file
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