wrsw_hal: removed V2 port calibration

b71f6f38 · Tomasz Wlostowski · Alessandro Rubini · db20cc97 · b71f6f38 · b71f6f38
Commit b71f6f38 authored Mar 05, 2012 by Tomasz Wlostowski Committed by Alessandro Rubini Mar 05, 2012
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Makefile userspace/wrsw_hal/Makefile +3 -3

driver_stuff.h userspace/wrsw_hal/driver_stuff.h +11 -0

hal_ports.c userspace/wrsw_hal/hal_ports.c +46 -19

No files found.
--- a/userspace/wrsw_hal/Makefile
+++ b/userspace/wrsw_hal/Makefile
@@ -12,11 +12,11 @@ WR_INCLUDE = $(WR_INSTALL_ROOT)/include
 WR_LIB = $(WR_INSTALL_ROOT)/lib

 CFLAGS = -g -Wall -DDEBUG \
-	-I. -I../include -I../3rdparty/include -I$(WR_INCLUDE)
+	-I. -I../../../ptp-noposix-v3/libwripc -I../include -I../3rdparty/include -I$(WR_INCLUDE)

 LDFLAGS = -L$(WR_INSTALL_ROOT)/lib -L../3rdparty/lib -L$(WR_LIB) \
-	-L../rubi-repos/ptp-noposix \
-	-lswitchhw -lwripc -llua -lm
+	-L../../../ptp-noposix-v3 -L../libswitchhw \
+	 -lwripc -llua -lm -ldl -lswitchhw

 all: $(BINARY)


--- a/userspace/wrsw_hal/driver_stuff.h
+++ b/userspace/wrsw_hal/driver_stuff.h
+
+#define PRIV_IOCGCALIBRATE (SIOCDEVPRIVATE + 1)
+#define PRIV_IOCGGETPHASE (SIOCDEVPRIVATE + 2)
+#define PRIV_IOCREADREG (SIOCDEVPRIVATE + 3)
+#define PRIV_IOCPHYREG (SIOCDEVPRIVATE + 4)
+
+#define NIC_READ_PHY_CMD(addr)  (((addr) & 0xff) << 16)
+#define NIC_RESULT_DATA(val) ((val) & 0xffff)
+#define NIC_WRITE_PHY_CMD(addr, value)  ((((addr) & 0xff) << 16) \
+ | (1 << 31) \
+ | ((value) & 0xffff))
--- a/userspace/wrsw_hal/hal_ports.c
+++ b/userspace/wrsw_hal/hal_ports.c
@@ -13,6 +13,7 @@
 #include <sys/ioctl.h>
 #include <linux/if_ether.h>
 #include <linux/if_arp.h>
+#include <linux/if.h>

 #include <wr_ipc.h>

@@ -29,6 +30,7 @@

 #include "wrsw_hal.h"
 #include "hal_exports.h"
+#include "driver_stuff.h"

 #define MAX_PORTS 64

@@ -340,15 +342,46 @@ static void port_locking_fsm(hal_port_state_t *p)
 }

 /* Updates the current value of the phase shift on a given port. Called by the main update function regularly. */
+struct wr_phase_req{
+	int valid;
+	uint32_t phase;
+};
+
 static void poll_dmtd(hal_port_state_t *p)
 {
+	struct ifreq ifr;
+	struct wr_phase_req preq;
+	
+	strncpy(ifr.ifr_name, p->name, sizeof(ifr.ifr_name));
+
+	ifr.ifr_data=  (void *)&preq;
+
+	if(ioctl(fd_raw, PRIV_IOCGGETPHASE, &ifr) < 0) return;
+	
+//	fprintf(stderr, "Poll: %d %d\n", preq.valid, preq.phase);
+	
 	/* FIXME: what should we do here? */
+	p->phase_val = (int)((double)preq.phase / 16384.0 * 16000.0);
+	p->phase_val_valid = preq.valid;
 }

-
-static uint16_t pcs_readl(int endpoint, uint8_t reg)
+uint32_t pcs_readl(hal_port_state_t *p, int reg)
 {
+	struct ifreq ifr;
+	uint32_t rv;
+	
+	strncpy(ifr.ifr_name, p->name, sizeof(ifr.ifr_name));

+	rv = NIC_READ_PHY_CMD(reg);
+	ifr.ifr_data = (void *)&rv;
+//	printf("raw fd %d name %s\n", fd_raw, ifr.ifr_name);
+	if(	ioctl(fd_raw, PRIV_IOCPHYREG, &ifr) < 0)
+	{
+		fprintf(stderr,"ioctl failed\n");
+	};
+	
+	printf("PCS_readl: reg %d data %x\n", reg, NIC_RESULT_DATA(rv));
+	return NIC_RESULT_DATA(rv);
 }


@@ -356,24 +389,7 @@ static uint16_t pcs_readl(int endpoint, uint8_t reg)
 static void calibration_fsm(hal_port_state_t *p)
 {

-/* Downlink ports are not supported yet.... Sorry... */
-	if(p->name[2] == 'd')
-	{
-		TRACE(TRACE_INFO,"Bypassing calibration for downlink port %s", p->name);
-		p->calib.tx_calibrated = 1;
-		p->calib.rx_calibrated = 1;
-		/* FIXME: use proper register names */
-		p->calib.delta_rx_phy = p->calib.phy_rx_min + ((pcs_readl(p->hw_index, 16) >> 4) & 0x1f) * 800;
-		p->calib.delta_tx_phy = p->calib.phy_tx_min;
-		p->tx_cal_pending = 0;
-		p->rx_cal_pending = 0;
-
-		return;
-	}

-/* Is there a calibration measurement in progress for this port? */
-
-/* no, not in V3 */
 }


@@ -406,6 +422,17 @@ static void port_fsm(hal_port_state_t *p)
 	{
 		if(link_up)
 		{
+		p->calib.tx_calibrated = 1;
+		p->calib.rx_calibrated = 1;
+		/* FIXME: use proper register names */
+		p->calib.delta_rx_phy = p->calib.phy_rx_min + ((pcs_readl(p, 16) >> 4) & 0x1f) * 800;
+		p->calib.delta_tx_phy = p->calib.phy_tx_min;
+
+		TRACE(TRACE_INFO,"Bypassing calibration for downlink port %s [dTx %d, dRx %d]", p->name, p->calib.delta_tx_phy, 	p->calib.delta_rx_phy);
+
+		p->tx_cal_pending = 0;
+		p->rx_cal_pending = 0;
+
 			TRACE(TRACE_INFO, "%s: link up", p->name);
 			p->state = HAL_PORT_STATE_UP;
 		}