usespace: libwr/ and include/: remove trailing space

This commit makes no changes, as shown by "git diff -w" before committing, but blank spaces at end-of-line make my editor scream (because I'm pedanting in not pushing those to the kernel). Signed-off-by: Alessandro Rubini <rubini@gnudd.com>

usespace: libwr/ and include/: remove trailing space
This commit makes no changes, as shown by "git diff -w" before committing, but blank spaces at end-of-line make my editor scream (because I'm pedanting in not pushing those to the kernel). Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
66d08b81 · Alessandro Rubini · 83882b90 · 66d08b81 · 66d08b81 · 66d08b81
Commit 66d08b81 authored Nov 19, 2014 by Alessandro Rubini
15 changed files
--- a/userspace/include/fpga_io.h
+++ b/userspace/include/fpga_io.h
@@ -28,7 +28,7 @@
 #define FPGA_BASE_PSTATS 0x58000
 /* HardWare Debugging Unit */
-#define FPGA_BASE_HWDU 	  0x59000 
+#define FPGA_BASE_HWDU 	  0x59000
 /* Endpoint  */
 #define FPGA_BASE_EP0 	   0x30000

--- a/userspace/libwr/Makefile
+++ b/userspace/libwr/Makefile
@@ -8,7 +8,7 @@ OBJS = trace.o init.o fpga_io.o util.o pps_gen.o i2c.o shw_io.o i2c_bitbang.o \
 LIB = libwr.a
-all: $(LIB) 
+all: $(LIB)
 $(LIB): $(OBJS)
 	$(AR) rc $@ $^

--- a/userspace/libwr/README
+++ b/userspace/libwr/README
 Switch V3 Hardware Library (libwr)
 -------------------------------
-Libwr is a collection of low-level userspace drivers for various 
+Libwr is a collection of low-level userspace drivers for various
 peripherals in the switch, which do not need kernel modules. These are:
 - Main FPGA (fpga_io.c) and CPU GPIO ports (pio.c), pin definitions (shw_io.c)
 - PPS generator (pps_gen.c, adjustment of time)

--- a/userspace/libwr/fan.c
+++ b/userspace/libwr/fan.c
@@ -169,8 +169,8 @@ static uint32_t tmp100_read_reg(int dev_addr, uint8_t reg_addr, int n_bytes)
 	uint32_t rv=0, i;
 	data[0] = reg_addr;
-	i2c_write(&fpga_sensors_i2c, dev_addr, 1, data); 
+	i2c_write(&fpga_sensors_i2c, dev_addr, 1, data);
-	i2c_read(&fpga_sensors_i2c, dev_addr, n_bytes, data); 
+	i2c_read(&fpga_sensors_i2c, dev_addr, n_bytes, data);
 	for(i=0; i<n_bytes;i++)
 	{
@@ -189,7 +189,7 @@ static void tmp100_write_reg(int dev_addr, uint8_t reg_addr, uint8_t value)
 	data[0] = reg_addr;
 	data[1] = value;
-	i2c_write(&fpga_sensors_i2c, dev_addr, 2, data); 
+	i2c_write(&fpga_sensors_i2c, dev_addr, 2, data);
 }

--- a/userspace/libwr/hal_client.c
+++ b/userspace/libwr/hal_client.c
@@ -62,17 +62,17 @@ int halexp_get_timing_state(hexp_timing_state_t *tstate)
 int halexp_client_try_connect(int retries, int timeout)
 {
 	for(;;) {
 		hal_ch = minipc_client_create(WRSW_HAL_SERVER_ADDR, MINIPC_FLAG_VERBOSE);
 		if (hal_ch == 0)
 			retries--;
-		else 
+		else
 			return 0;
 		if(!retries)
 			return -1;
 		usleep(timeout);
 	}

--- a/userspace/libwr/hwiu.c
+++ b/userspace/libwr/hwiu.c
@@ -46,7 +46,7 @@ int shw_hwiu_gwver(struct gw_info *info)
    printf("nwords: sw=%u, hw=%u, ver=%u, data=%x\n", info->nwords, HWIU_INFO_WORDS, info->struct_ver, data[0]);
    return -1;
  }
  //now read info words
  for(i=0; i<info->nwords; ++i) {
    if( hwiu_read_word(HWIU_INFO_WORDS_START+i, data+i+1) < 0 )

--- a/userspace/libwr/i2c.c
+++ b/userspace/libwr/i2c.c
@@ -33,7 +33,7 @@ void i2c_free(struct i2c_bus* bus)
 {
    if (!bus)
 	return;
    if (bus->type_specific)
 	shw_free(bus->type_specific);
@@ -59,18 +59,18 @@ int32_t i2c_scan(struct i2c_bus* bus, uint8_t* data)
 {
    if (!bus)
        return I2C_NULL_PARAM;
 //    const int devices = 128;
    int address;
    const int first_valid_address = 0;
    const int last_valid_address = 0x7f;
    memset((void*)data, 0, 16);		//16 bytes * 8 addresses per byte == 128 addresses
    int found = 0;
    for (address = first_valid_address; address <= last_valid_address; address++)
    {
 	int res = bus->scan(bus, address);

--- a/userspace/libwr/i2c_bitbang.c
+++ b/userspace/libwr/i2c_bitbang.c
@@ -30,7 +30,7 @@ int i2c_bitbang_init_bus(struct i2c_bus *bus)
 	shw_pio_setdir(priv->sda, 0);
 	priv->udelay = 50;
 	priv->timeout = 100;
 	//assign functions
 	bus->transfer = i2c_bitbang_transfer;
 	bus->scan = i2c_bitbang_scan;
@@ -52,7 +52,7 @@ static void mi2c_start(struct i2c_bitbang* bus)
       mi2c_pin_out(bus->scl, 0);
 }
-/* not used right now 
+/* not used right now
 static void mi2c_restart(struct i2c_bitbang* bus)
 {
       mi2c_pin_out(bus->sda, 1);
@@ -74,7 +74,7 @@ static int mi2c_write_byte(struct i2c_bitbang* bus, uint8_t data)
 {
       int ack = 0;
       int b;
       for (b = 0; b < 8; b++)
       {
       	mi2c_pin_out(bus->sda, data & 0x80);	//set MSB to SDA
@@ -82,18 +82,18 @@ static int mi2c_write_byte(struct i2c_bitbang* bus, uint8_t data)
       	mi2c_pin_out(bus->scl, 0);
       	data <<= 1;
       }
       mi2c_pin_out(bus->sda, 1);	//go high
       mi2c_pin_out(bus->scl, 1);	//toggle clock
       shw_pio_setdir(bus->sda, PIO_IN);		//let SDA float
       shw_udelay(I2C_DELAY);
       ack = shw_pio_get(bus->sda);
       mi2c_pin_out(bus->scl, 0);
    //   shw_pio_setdir(bus->sda, PIO_OUT_1);	//turn on output
       shw_udelay(I2C_DELAY);
       return (ack == 0) ? 1: 0;
 }
@@ -106,7 +106,7 @@ static uint8_t mi2c_get_byte(struct i2c_bitbang *bus, int ack)
 	mi2c_pin_out(bus->scl, 0);
 	shw_pio_setdir(bus->sda, PIO_IN);		//let SDA float so we can read it
 	for (i=0;i<8;i++)
 	{
 		mi2c_pin_out(bus->scl, 1);
@@ -117,12 +117,12 @@ static uint8_t mi2c_get_byte(struct i2c_bitbang *bus, int ack)
 	}
 	//send ACK or NAK
-	mi2c_pin_out(bus->sda, ack ? 0 : 1);	
+	mi2c_pin_out(bus->sda, ack ? 0 : 1);
 	shw_udelay(I2C_DELAY);
 	mi2c_pin_out(bus->scl, 1);		//generate SCL pulse for slave to read ACK/NACK
 	mi2c_pin_out(bus->scl, 0);
 	return result;
 }
@@ -157,25 +157,25 @@ static int32_t i2c_bitbang_scan(struct i2c_bus* bus, uint32_t address)
 	return state ? 1: 0;
 }
 static int i2c_bitbang_transfer(i2c_bus_t* bus, uint32_t address, uint32_t to_write, uint32_t to_read, uint8_t* data)
 {
 	if (!bus)
 		return I2C_NULL_PARAM;
 	if (bus->type != I2C_TYPE_BITBANG)
 		return I2C_BUS_MISMATCH;
 	//TRACE(TRACE_INFO,"%s (0x%x) @ 0x%x: w=%d/r=%d; cmd=%d d=%d (0b%s)",bus->name,bus,address,to_write,to_read,data[0],data[1],shw_2binary(data[1]));
 	struct i2c_bitbang* ts = (struct i2c_bitbang*)bus->type_specific;
 	int sent = 0;
 	int rcvd = 0;
 	int ack = 0;
 	uint32_t i;
 	if (to_write > 0)
 	{
 		mi2c_start(ts);
@@ -184,7 +184,7 @@ static int i2c_bitbang_transfer(i2c_bus_t* bus, uint32_t address, uint32_t to_wr
 		{
 			mi2c_stop(ts);
 			return I2C_DEV_NOT_FOUND;				//the device did not ack it's address
-		}		
+		}
 		for (i=0; i < to_write; i++)
 		{
 			ack = mi2c_write_byte(ts, data[i]);		//write data
@@ -197,7 +197,7 @@ static int i2c_bitbang_transfer(i2c_bus_t* bus, uint32_t address, uint32_t to_wr
 		}
 		mi2c_stop(ts);
 	}
 	if (to_read)
 	{
 		mi2c_start(ts);
@@ -209,7 +209,7 @@ static int i2c_bitbang_transfer(i2c_bus_t* bus, uint32_t address, uint32_t to_wr
 		}
 		uint32_t last_byte = to_read - 1;
 		for (i=0; i < to_read; i++)
 		{
 			data[i] = mi2c_get_byte(ts, i != last_byte);		//read data, ack until the last byte
@@ -217,7 +217,7 @@ static int i2c_bitbang_transfer(i2c_bus_t* bus, uint32_t address, uint32_t to_wr
 		}
 		mi2c_stop(ts);
 	}
 	return sent+rcvd;
 }
--- a/userspace/libwr/i2c_bitbang.h
+++ b/userspace/libwr/i2c_bitbang.h
 /*
 	i2c_bitbang.h
-	2012 CERN B.Bielawski 
+	2012 CERN B.Bielawski
 */
 #ifndef I2C_CPU_BB_H

--- a/userspace/libwr/i2c_fpga_reg.c
+++ b/userspace/libwr/i2c_fpga_reg.c
@@ -143,7 +143,7 @@ static int32_t i2c_fpga_reg_transfer(struct i2c_bus* bus, uint32_t i2c_address,
 		return I2C_NULL_PARAM;
 	if (bus->type != I2C_BUS_TYPE_FPGA_REG)
 		return I2C_BUS_MISMATCH;
 	i2c_fpga_reg_t* ts = (i2c_fpga_reg_t*)bus->type_specific;
 	uint32_t fpga_address = ts->base_address;
@@ -168,10 +168,10 @@ static int32_t i2c_fpga_reg_transfer(struct i2c_bus* bus, uint32_t i2c_address,
 				mi2c_sel_if(fpga_address, ts->if_num, 0);
 				return I2C_NO_ACK_RCVD;
 			}
-			sent++; 
+			sent++;
 		}
 	}
 	if (to_read) {
 		ack = mi2c_start(fpga_address, i2c_address, I2C_READ);
 		if (!ack) {		//NAK

--- a/userspace/libwr/i2c_fpga_reg.h
+++ b/userspace/libwr/i2c_fpga_reg.h
 /*
 	i2c_fpga_reg.h
-	2012 CERN B.Bielawski 
+	2012 CERN B.Bielawski
 */
 #ifndef I2C_FPGA_REG_H

--- a/userspace/libwr/i2c_sfp.c
+++ b/userspace/libwr/i2c_sfp.c
@@ -396,15 +396,15 @@ void shw_sfp_gpio_init(void)
 	struct i2c_bus *bus = &i2c_buses[WR_FPGA_BUS0];
 	/* configure the pins as outputs */
-	i2c_transfer(bus, addr, 2, 0, conf_output); 
+	i2c_transfer(bus, addr, 2, 0, conf_output);
-	i2c_transfer(bus, addr, 2, 0, set_output); 
+	i2c_transfer(bus, addr, 2, 0, set_output);
 	bus = &i2c_buses[WR_FPGA_BUS1];
 	for (i = 0; i < 8; i++) {
-		i2c_transfer(bus, addr + i, 2, 0, conf_output); 
+		i2c_transfer(bus, addr + i, 2, 0, conf_output);
-		i2c_transfer(bus, addr + i, 2, 0, set_output); 
+		i2c_transfer(bus, addr + i, 2, 0, set_output);
 	}
 	for(i=0; i<18;i++)
 	{
 		shw_sfp_set_led_synced(i, 1);
@@ -420,7 +420,7 @@ void shw_sfp_gpio_init(void)
 		shw_udelay(7000);
 	}
 }
 void shw_sfp_gpio_set(int num, uint8_t state)
@@ -448,8 +448,8 @@ void shw_sfp_gpio_set(int num, uint8_t state)
 	/* Read current state of pins */
-	i2c_transfer(bus, addr, 1, 0, send); 
+	i2c_transfer(bus, addr, 1, 0, send);
-	i2c_transfer(bus, addr, 0, 1, &curr); 
+	i2c_transfer(bus, addr, 0, 1, &curr);
 	//TRACE(TRACE_INFO,"%d: 0x%x 0x%x s=%d, send=%d,%d c=%d, \n",num,bus,addr,state,send[0],send[1],&curr);
@@ -468,7 +468,7 @@ void shw_sfp_gpio_set(int num, uint8_t state)
 		curr |= SFP_TX_DISABLE_MASK(top);
 	send[1] = curr;
-	i2c_transfer(bus, addr, 2, 0, send); 
+	i2c_transfer(bus, addr, 2, 0, send);
 	//TRACE(TRACE_INFO,"%d: 0x%x 0x%x s=%d, send=%d,%d c=%d, \n",num,bus,addr,state,send[0],send[1],curr);
 }
@@ -497,8 +497,8 @@ uint8_t shw_sfp_gpio_get(int num)
 	send[0] = 0x1;
 	/* Read current state of pins */
-	i2c_transfer(bus, addr, 1, 0, send); 
+	i2c_transfer(bus, addr, 1, 0, send);
-	i2c_transfer(bus, addr, 0, 1, &curr); 
+	i2c_transfer(bus, addr, 0, 1, &curr);
 	if (curr & SFP_LED_LINK_MASK(top))
 		out |= SFP_LED_LINK;

--- a/userspace/libwr/libshw_i2c.c
+++ b/userspace/libwr/libshw_i2c.c
@@ -22,7 +22,7 @@ int32_t wrswhw_pca9554_get_input(struct i2c_bus* bus, uint32_t address)
    int result = i2c_transfer(bus, address, 1, 0, &r);
    if (result < 0)
 	return result;
    //read one byte
    result = i2c_transfer(bus,address, 0, 1, &r);
    if (result < 0)
@@ -36,10 +36,10 @@ int wrswhw_pca9554_set_output_bits(struct i2c_bus* bus, uint32_t address, uint8_
    int result = wrswhw_pca9554_get_input(bus, address);
    if (result < 0)
 	return result;
    result |= value;	//or input bits
    result &= 0xFF;	//leave only 8 LSBs
    return wrswhw_pca9554_set_output_reg(bus, address, result);
 }
@@ -48,10 +48,10 @@ int wrswhw_pca9554_clear_output_bits(struct i2c_bus* bus, uint32_t address, uint
    int result = wrswhw_pca9554_get_input(bus, address);
    if (result < 0)
 	return result;
    result &= ~value;	//remove bits we don't need
    result &= 0xFF;	//leave only 8 LSBs
    return wrswhw_pca9554_set_output_reg(bus, address, result);
 }
--- a/userspace/libwr/pio.c
+++ b/userspace/libwr/pio.c
@@ -90,14 +90,14 @@ extern const pio_pin_t* _all_fpga_gpio_pins[];
 void shw_pio_toggle_pin(pio_pin_t* pin, uint32_t udelay)
 {
    while (1)
-    {    
+    {
 	shw_pio_set(pin, 0);
 	shw_udelay(udelay);
 	shw_pio_set(pin, 1);
 	shw_udelay(udelay);
    }
 }
 void shw_pio_configure(const pio_pin_t *pin)
 {
    uint32_t mask = (1<<pin->pin);
@@ -148,8 +148,8 @@ void shw_pio_configure(const pio_pin_t *pin)
            _writel(base + PIO_ODR, mask);	// select input
        }
        break;
    case PIO_FPGA:
        ddr = _readl(base + FPGA_PIO_REG_DDR);
@@ -166,7 +166,7 @@ void shw_pio_configure(const pio_pin_t *pin)
        _writel(base + FPGA_PIO_REG_DDR, ddr);
        break;
    }		//switch
 }

--- a/userspace/libwr/pps_gen.c
+++ b/userspace/libwr/pps_gen.c
@@ -47,7 +47,7 @@ int shw_pps_gen_init()
 /* Adjusts the nanosecond (refclk cycle) counter by atomically adding (how_much) cycles. */
 int shw_pps_gen_adjust(int counter, int64_t how_much)
 {
-  TRACE(TRACE_INFO, "Adjust: counter = %s [%c%lld]", 
+  TRACE(TRACE_INFO, "Adjust: counter = %s [%c%lld]",
  	counter == PPSG_ADJUST_SEC ? "seconds" : "nanoseconds", how_much<0?'-':'+', abs(how_much));
 	if(counter == PPSG_ADJUST_NSEC)
@@ -88,7 +88,7 @@ void shw_pps_gen_read_time(uint64_t *seconds, uint32_t *nanoseconds)
 {
 	uint32_t ns_cnt;
 	uint64_t sec1, sec2;
 	do {
 		sec1 = (uint64_t)ppsg_read(CNTR_UTCLO) | (uint64_t)ppsg_read(CNTR_UTCHI) << 32;
 		ns_cnt = ppsg_read(CNTR_NSEC);