problem with high clk2 frequencies
CLK2 generation works fine for 10MHz and other "low" frequencies. However, trying to set the frequency to some "higher" value like 200MHz creates the clock signal that differs from expectations. E.g. for 200MHz, generated signal is 250MHz despite the correct output from the wrs_auxclk tool:
wrs# wrs_auxclk --freq 200 --cshift 0
Calculated settings:
period: 5 ns (200 MHz)
high: 1 ns; low: 1 ns
duty: 0.400000
coarse shift: 0
PPS shift: 0 taps
Signal delay: 0 taps