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White Rabbit Switch - Hardware
Commit b559b497 authored by jgabriel's avatar jgabriel
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Preliminary SCB Schematic and PCB version.

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circuit_board/wrs_v3/LIBS/viewdraw.ini 0 → 100644
View file @ b559b497
| Viewdraw initialization file for ePD Version 2005
|
| (c) Copyright 2005 Mentor Graphics Corporation
||
|
| Set the default display characteristics for each object
|
|
| Colors
| ------------------------------------------------------------------
|
| 0 Black | 4 Red | 8 Gray | 12 Lt. Red
| 1 Blue | 5 Magenta | 9 Lt. Blue | 13 Lt. Magenta
| 2 Green | 6 Brown | 10 Lt. Green | 14 Yellow
| 3 Cyan | 7 Lt. Gray | 11 Lt. Cyan | 15 White
|
|
| Fillstyles:
| ------------------------------------------------------------------
|
| 0 Hollow | 1 Solid
|
|
| Object Color Fillstyle Linestyle
| or Font
| ------ ----- --------- ---------
|
NET 12 1 0
COMPONENT 15 0 0
ATTRIBUTE 14 0 0
LABEL 15 0 0
PIN 3 0 0
BOX 2 0 0
LINE 2 0 0
CIRCLE 2 0 0
ARC 2 0 0
TEXT 10 0 0
|
|
| set the display characteristics for the selection layer
|
SELECTION_LAYER 15 0 0
|
| set the display characteristics for the border layer
|
BORDER_LAYER 15 0 0
|
| set the display characteristics for the value layer
|
VALUE_LAYER 7 0 0
|
| set the display characteristics for the annotation layer
|
ANNO_LAYER 7 0 0
|
| set the background color
|
|5.0 WINDOW_BACKGROUND 0 0 0
|
|
| Default values
|
GRID 10 | Grid spacing (units)
DOTSIZE 5 | Solder dot radius (units)
BUS_DOTSIZE 12 | Bus solder dot radius (units)
BOXSIZE 5 | Dangling joint box width (units)
TEXTSIZE 10 | Text size (units)
TEXTORIGIN 3 | Text origin
BUSWIDTH 4 | Bus half-width (units)
BUBBLESIZE 5 | Bubble size on pins (units)
AUTOLOG 10 | Autolog value (number of Viewdraw commands to
| hold before writing to log file)
SDISTANCE 10 | Selection distance (units)
ADISTANCE 20 | Avoidance distance (units)
SHEETSIZE 1 | Sheet size.
| 0 = ASIZE, 1 = BSIZE, 2 = CSIZE, 3 = DSIZE,
| 4 = ESIZE, 5 = A4, 6 = A3, 7 = A2,
| 8 = A1, 9 = A0
| 10 = ZSIZE (requires width and height)
| Ex: SHEETSIZE 10 200 200
ROUTE 2 | Net routing.
| 0 = Straight, 1 = Orthogonal, 2 = Avoidance
SCOPE 0 | Scope for labels 0 = Local, 1 = Global
TEXT_THRESHOLD 3 | Threshold (units)
NEW_ATTR_VIS 1 | New attribute and value visibility
| 1 = Name and value visible,
| 2 = Name only visible
| 3 = Value only visible
BLOCKTYPE 0 | Default block type
| 0 = Composite, 1 = Module, 2 = annotate, 3 = pin
UNDO 16 | number of commands to undo
|
| Default modes. (1 = On or Yes; 0 = Off or No.)
|
GRIDON 1 | Grid display.
BORDERON 1 | Border display.
HEADERON 1 | Header display.
COMPTEXTON 1 | Component text, labels and attributes.
TEXTON 1 | Text.
ATTRON 1 | Attributes
LABELON 1 | labels
DETAIL 1 | detail ** Changed at 5.0 **
SNAPTOPIN 1 | snap to pin
UNIQUE_LABEL 0 | create unique labels on copy
VALUESON 1 | display simulation values (or generic b/a)
CONTEXT_WINDOW 0 | display context window ** Changed at 5.0 **
NAMESON 0 | display internal names
SORTON 1 | alphabetically sort dialog entries
PNUMSON 1 | display pin numbers
RNUMSON 1 | display refdes
DEFSHEET 0 | search for sheet template for new sheets
XTRAERRS 1 | print out all errors in checker
DBOXON 0 | pick names from dialog boxes
STROKES 1 | executing commands using strokes
DYNAMIC_PANNING 1 | moving with dynamic panning
|
| Turning this on will enable case preservation for attribute values. This
| may sound interesting, but it can raise havoc with downstream tools, as
| well as with older tools that don't supprt mixed-case.
|
PRESERVE_CASE 1 | turn on case preservation
|
| This is an example of how to add an attribute to the mixed case list. In
| this example, any attribute named DATASHEET would be allowed to have a
| mixed-case value.
|
ALLOW_VALUE_MIXED #
|5.0 DB_ERR_VERBOSE 1 | verbose database reader error messages
|5.0 FUBPINTYPEON 1 | create PINTYPE att as FUB pins created
|5.0 SELNAMEON 0 | display selected object's name in LL
NETNAME VDD | Upon creation, VDD will have global scope.
NETNAME GND | Upon creation, GND will have global scope.
|SYMBOL_QUALIFIERS \D | Demorgan
|SYMBOL_QUALIFIERS \C | Conventional
|SYMBOL_QUALIFIERS \A | Ansi
|SYMBOL_QUALIFIERS \P | Package
ATTR_RESET SS#1 | Never copy this SCICARD attribute
ATTR_RESET SS#2 | Never copy this SCICARD attribute
ATTR_RESET ALL_ID | Never copy this ALLEGRO attribute
ATTR_RESET GEN_ID | Never copy this ALLEGRO attribute
ATTR_RESET DIFF_PAIR | Never copy the DIFF_PAIR attribute
ATTR_RESET REFDES SYMBOL_VALUE | Reset REFDES attribute value from symbol
|8.0 SHOW_TOOLTIP_FOR REFDES
|8.0 COMPONENT_TOOLTIPS 1
|5.0 COARSE_GRID 0
|5.0 DYNAMIC_XY 0
|5.0 BEGIN_NETS_IN_SPACE 0
|5.0 OATS 1
|5.0 ATTR_PROMOTE BIT
|7.5 PARTIAL_UNLIMITED_TEXT_LENGTH 1
|8.0 IO_PINS builtin:in.1
|8.0 IO_PINS builtin:out.1
|8.0 IO_PINS builtin:bi.1
|8.0 ONSHEET_PINS builtin:onsheet.1
|8.0 OFFSHEET_PINS builtin:offsheet.1
|8.0 POWER_PINS builtin:pwr.1
|8.0 GROUND_PINS builtin:gnd.1
|8.1 SERIES_RESISTOR_SYM analog:res.1
|8.1 PARALLEL_RESISTOR_SYM analog:res.2
|8.1 CAPACITOR_SYM analog:cap.1
|8.1 GROUND_SYM builtin:gnd.1
|8.1 POWER_SYM builtin:pwr.1
| Design Directories
| ------------------
|
| Format: DIR [DirType(s)] DirPath (LibName)
|
| DirType: p or pw - primary / writable
| w - writable (read/write)
| r - read-only
| m or rm - read-only megafile
|
| DirPath: directory specification ("." for current directory relative path)
|
| LibName: library name aka library alias or VHDL library name (optional)
| 32 characters or less. Must begin with a letter.
|
| examples:
|
| DIR [p] .
| DIR [r] /libs/74ls (vl74ls)
| DIR [r] /libs/builtin (builtin)
| DIR [w] ./under/development/alu (newalu)
|
DIR [p] .
circuit_board/wrs_v3/SCB/CPU_100M_Ethernet.Harness 0 → 100644
View file @ b559b497
ETH_100MHz=SHIELD,TX_P,TX_N,RX_P,RX_N,LED_LINK,LED_ACT
circuit_board/wrs_v3/SCB/CPU_IO_Ports.Harness 0 → 100644
View file @ b559b497
CPU_SSC=RF1,RK1,RD1,TD1,TK1,TF1
SPI0=SPI0_MISO,SPI0_MOSI,SPI0_SPCK,SPI0_NPCS0
SPI1=SPI1_MISO,SPI1_MOSI,SPI1_SPCK,SPI1_NPCS0
circuit_board/wrs_v3/SCB/CPU_JTAG_Power_PLL.Harness 0 → 100644
View file @ b559b497
CPU_JTAG=JNRST,JTDO,JRTCK,JTCK,JTMS,JTDI,JNTRST
circuit_board/wrs_v3/SCB/CPU_Memory.Harness 0 → 100644
View file @ b559b497
SPI0=SPI0_NPCS0,SPI0_SPCK,SPI0_MOSI,SPI0_MISO
circuit_board/wrs_v3/SCB/Connectors.Harness 0 → 100644
View file @ b559b497
CPU_JTAG=JNTRST,JTDI,JTMS,JTCK,JRTCK,JTDO,JNRST
CPU_SSC=TF1,TK1,TD1,RD1,RK1,RF1
ETH_100MHz=LED_ACT,LED_LINK,RX_N,RX_P,TX_N,TX_P,SHIELD
FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDI,FPGA_TDO
MGTRX112PN=MGTRX112_0_P,MGTRX112_0_N,MGTRX112_1_P,MGTRX112_1_N,MGTRX112_2_P,MGTRX112_2_N,MGTRX112_3_P,MGTRX112_3_N
MGTRX113PN=MGTRX113_0_P,MGTRX113_0_N,MGTRX113_1_P,MGTRX113_1_N,MGTRX113_2_P,MGTRX113_2_N,MGTRX113_3_P,MGTRX113_3_N
MGTRX114PN=MGTRX114_0_P,MGTRX114_0_N,MGTRX114_1_P,MGTRX114_1_N,MGTRX114_2_P,MGTRX114_2_N,MGTRX114_3_P,MGTRX114_3_N
MGTRX115PN=MGTRX115_0_P,MGTRX115_0_N,MGTRX115_1_P,MGTRX115_1_N,MGTRX115_2_P,MGTRX115_2_N,MGTRX115_3_P,MGTRX115_3_N
MGTRX116PN=MGTRX116_0_P,MGTRX116_0_N,MGTRX116_1_P,MGTRX116_1_N,MGTRX116_2_P,MGTRX116_2_N,MGTRX116_3_P,MGTRX116_3_N
MGTTX112PN=MGTTX112_0_P,MGTTX112_0_N,MGTTX112_1_P,MGTTX112_1_N,MGTTX112_2_P,MGTTX112_2_N,MGTTX112_3_P,MGTTX112_3_N
MGTTX113PN=MGTTX113_0_P,MGTTX113_0_N,MGTTX113_1_P,MGTTX113_1_N,MGTTX113_2_P,MGTTX113_2_N,MGTTX113_3_P,MGTTX113_3_N
MGTTX114PN=MGTTX114_0_P,MGTTX114_0_N,MGTTX114_1_P,MGTTX114_1_N,MGTTX114_2_P,MGTTX114_2_N,MGTTX114_3_P,MGTTX114_3_N
MGTTX115PN=MGTTX115_0_P,MGTTX115_0_N,MGTTX115_1_P,MGTTX115_1_N,MGTTX115_2_P,MGTTX115_2_N,MGTTX115_3_P,MGTTX115_3_N
MGTTX116PN=MGTTX116_0_P,MGTTX116_0_N,MGTTX116_1_P,MGTTX116_1_N,MGTTX116_2_P,MGTTX116_2_N,MGTTX116_3_P,MGTTX116_3_N
RS232_MNG=RS232_MNG_TXD,RS232_MNG_RTS,RS232_MNG_RXD,RS232_MNG_CTS
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N
circuit_board/wrs_v3/SCB/External WatchDogs.Harness 0 → 100644
View file @ b559b497
FPGA_WD=FPGA_WD_SCL,FPGA_WD_SDA,FPGA_WD_INT,FPGA_WD_PROGRAM
circuit_board/wrs_v3/SCB/FPGA_CLKs.Harness 0 → 100644
View file @ b559b497
DAC_CONTROL=DAC_REF_SCLK,DAC_REF_SYNC,DAC_REF_DIN,DAC_DMTD_SCLK,DAC_DMTD_SYNC,DAC_DMTD_DIN
circuit_board/wrs_v3/SCB/FPGA_Configuration.Harness 0 → 100644
View file @ b559b497
FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDI,FPGA_TDO
FPGA_WD=FPGA_WD_SCL,FPGA_WD_SDA,FPGA_WD_INT,FPGA_WD_PROGRAM
QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N
circuit_board/wrs_v3/SCB/FPGA_GTX.Harness 0 → 100644
View file @ b559b497
MGTREFCLK=MGTREFCLK112_P,MGTREFCLK112_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK116_P,MGTREFCLK116_N
MGTRX112PN=MGTRX112_0_P,MGTRX112_0_N,MGTRX112_1_P,MGTRX112_1_N,MGTRX112_2_P,MGTRX112_2_N,MGTRX112_3_P,MGTRX112_3_N
MGTRX113PN=MGTRX113_0_P,MGTRX113_0_N,MGTRX113_1_P,MGTRX113_1_N,MGTRX113_2_P,MGTRX113_2_N,MGTRX113_3_P,MGTRX113_3_N
MGTRX114PN=MGTRX114_0_P,MGTRX114_0_N,MGTRX114_1_P,MGTRX114_1_N,MGTRX114_2_P,MGTRX114_2_N,MGTRX114_3_P,MGTRX114_3_N
MGTRX115PN=MGTRX115_0_P,MGTRX115_0_N,MGTRX115_1_P,MGTRX115_1_N,MGTRX115_2_P,MGTRX115_2_N,MGTRX115_3_P,MGTRX115_3_N
MGTRX116PN=MGTRX116_0_P,MGTRX116_0_N,MGTRX116_1_P,MGTRX116_1_N,MGTRX116_2_P,MGTRX116_2_N,MGTRX116_3_P,MGTRX116_3_N
MGTTX112PN=MGTTX112_0_P,MGTTX112_0_N,MGTTX112_1_P,MGTTX112_1_N,MGTTX112_2_P,MGTTX112_2_N,MGTTX112_3_P,MGTTX112_3_N
MGTTX113PN=MGTTX113_0_P,MGTTX113_0_N,MGTTX113_1_P,MGTTX113_1_N,MGTTX113_2_P,MGTTX113_2_N,MGTTX113_3_P,MGTTX113_3_N
MGTTX114PN=MGTTX114_0_P,MGTTX114_0_N,MGTTX114_1_P,MGTTX114_1_N,MGTTX114_2_P,MGTTX114_2_N,MGTTX114_3_P,MGTTX114_3_N
MGTTX115PN=MGTTX115_0_P,MGTTX115_0_N,MGTTX115_1_P,MGTTX115_1_N,MGTTX115_2_P,MGTTX115_2_N,MGTTX115_3_P,MGTTX115_3_N
MGTTX116PN=MGTTX116_0_P,MGTTX116_0_N,MGTTX116_1_P,MGTTX116_1_N,MGTTX116_2_P,MGTTX116_2_N,MGTTX116_3_P,MGTTX116_3_N
circuit_board/wrs_v3/SCB/FPGA_PLLs.Harness 0 → 100644
View file @ b559b497
MGTREFCLK=MGTREFCLK116_P,MGTREFCLK116_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK112_P,MGTREFCLK112_N
PLL_CONTROL=PLL_SDI,PLL_SDO,PLL_SCLK,PLL_REFSEL,PLL_RESET,PLL_LOCK,PLL_STAT,PLL_CS
QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N
circuit_board/wrs_v3/SCB/FPGA_QDRII.Harness 0 → 100644
View file @ b559b497
qdr2_1_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
qdr2_2_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
circuit_board/wrs_v3/SCB/Power_Supply.Harness 0 → 100644
View file @ b559b497
Power-Good=+1V5_PG,+1V0_PG,+1V0_GTX_PG,+3V3_OSC_PG,+2V5_OSC_PG,+1V2_GTX_PG,+2V5_PG,+1V8_PG
circuit_board/wrs_v3/SCB/QDRII_mem.Harness 0 → 100644
View file @ b559b497
qdr2_1_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
qdr2_2_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
circuit_board/wrs_v3/SCB/RS232_and_USB_ports.Harness 0 → 100644
View file @ b559b497
RS232_MNG=RS232_MNG_TXD,RS232_MNG_RTS,RS232_MNG_RXD,RS232_MNG_CTS
circuit_board/wrs_v3/SCB/SCB.PrjPCB 0 → 100644
View file @ b559b497
This diff is collapsed.
circuit_board/wrs_v3/SCB/SMI_Link_7-12.Harness 0 → 100644
View file @ b559b497
Power-Good=+1V5_PG,+1V0_PG,+1V0_GTX_PG,+3V3_OSC_PG,+2V5_OSC_PG,+1V2_GTX_PG,+2V5_PG,+1V8_PG
SPI1=SPI1_MISO,SPI1_MOSI,SPI1_SPCK,SPI1_NPCS0
circuit_board/wrs_v3/SCB/uTCA_Tongue3.Harness 0 → 100644
View file @ b559b497
DAC_CONTROL=DAC_DMTD_DIN,DAC_DMTD_SYNC,DAC_DMTD_SCLK,DAC_REF_DIN,DAC_REF_SYNC,DAC_REF_SCLK
PLL_CONTROL=PLL_CS,PLL_STAT,PLL_LOCK,PLL_RESET,PLL_REFSEL,PLL_SCLK,PLL_SDO,PLL_SDI
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