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White Rabbit Switch - Hardware
Commit 44810b61 authored by Nico Coesel's avatar Nico Coesel Committed by Grzegorz Daniluk
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SCB 3.4.1 by OPNT

parent 6f5ce206
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circuit_board/wrs_v3/SCB_SAM9G45/CHANGES.txt
View file @ 44810b61
SCB Changes from V3.4 to V3.4.1:
===============================
* J3 (the black connector on the right) is always fitted and J5 & J6 are added.
* J6 is a u.FL connector to which the clock output of the Low-jitter-daughterboard can be connected.
* J5 is used to select between the existing oscillator or the Low-jitter-daughterboard.
* Replacement of obsolete components (most notably a different NAND flash)
SCB Changes from V3.3 to V3.4:
===============================
......
circuit_board/wrs_v3/SCB_SAM9G45/Connectors.Harness
View file @ 44810b61
......@@ -14,4 +14,4 @@ MGTTX114PN=MGTTX114_0_P,MGTTX114_0_N,MGTTX114_1_P,MGTTX114_1_N,MGTTX114_2_P,MGTT
MGTTX115PN=MGTTX115_0_P,MGTTX115_0_N,MGTTX115_1_P,MGTTX115_1_N,MGTTX115_2_P,MGTTX115_2_N,MGTTX115_3_P,MGTTX115_3_N
MGTTX116PN=MGTTX116_0_P,MGTTX116_0_N,MGTTX116_1_P,MGTTX116_1_N,MGTTX116_2_P,MGTTX116_2_N,MGTTX116_3_P,MGTTX116_3_N
RS232_MNG=RS232_MNG_TXD,RS232_MNG_RXD,RS232_FPGA_TXD,RS232_FPGA_RXD
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N,MINIBACKPLANE_CLK_P,MINIBACKPLANE_CLK_N
uTCA_CLK=uTCA_TONGUE2_CLK1_P,uTCA_TONGUE2_CLK1_N,uTCA_TONGUE2_CLK2_P,uTCA_TONGUE2_CLK2_N,miniBACKPLANE_CLK_P,miniBACKPLANE_CLK_N
circuit_board/wrs_v3/SCB_SAM9G45/FPGA_PLLs.Harness deleted 100644 → 0
View file @ 6f5ce206
MGTREFCLK=MGTREFCLK116_P,MGTREFCLK116_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK112_P,MGTREFCLK112_N
PLL_CONTROL=PLL_SYNC,PLL_SDI,PLL_SDO,PLL_SCLK,PLL_REFSEL,PLL_RESET,PLL_LOCK,PLL_STAT,PLL_CS
QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N
circuit_board/wrs_v3/SCB_SAM9G45/Peripherals_Control.Harness deleted 100644 → 0
View file @ 6f5ce206
DAC_CONTROL=DAC_DMTD_DIN,DAC_DMTD_SYNC,DAC_DMTD_SCLK,DAC_REF_DIN,DAC_REF_SYNC,DAC_REF_SCLK
PLL_CONTROL=PLL_CS,PLL_STAT,PLL_LOCK,PLL_RESET,PLL_REFSEL,PLL_SCLK,PLL_SDO,PLL_SDI,PLL_SYNC,CLK1_SEL
Power-Good=+1V0_GTX_PG,+3V3_PLL_PG,+2V5_PLL_PG,+1V2_GTX_PG,+3V3_PG,+1V2_CPU_PG
SPI1=SPI1_MISO,SPI1_MOSI,SPI1_SPCK,SPI1_NPCS0
circuit_board/wrs_v3/SCB_SAM9G45/SCB.Dat 0 → 100644
View file @ 44810b61
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circuit_board/wrs_v3/SCB_SAM9G45/SCB.PrjPCB
View file @ 44810b61
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circuit_board/wrs_v3/SCB_SAM9G45/SCB_PLLs.Harness
View file @ 44810b61
MGTREFCLK=MGTREFCLK116_P,MGTREFCLK116_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK112_P,MGTREFCLK112_N
PLL_CLKS=REF_CLK_P,REF_CLK_N,AUX_CLK_P,AUX_CLK_N
PLL_CONTROL=PLL_SYNC,PLL_SDI,PLL_SDO,PLL_SCLK,PLL_REFSEL,PLL_RESET,PLL_LOCK,PLL_STAT,PLL_CS,CLK1_SEL,CLK_EN
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N,MINIBACKPLANE_CLK_P,MINIBACKPLANE_CLK_N
uTCA_CLK=uTCA_TONGUE2_CLK1_P,uTCA_TONGUE2_CLK1_N,uTCA_TONGUE2_CLK2_P,uTCA_TONGUE2_CLK2_N,miniBACKPLANE_CLK_P,miniBACKPLANE_CLK_N
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