Reset timing of CDCM61004
The CDCM61004 PLL is quite sensitive to the timing between startup of the reference oscillator and the moment its VCO is calibrated. In Issues with output incorrect PLL output frequency have been reported by GSI (using the same PLL).
This problem is also related to similar issue in SPEC project.
We checked the startup waveforms (see attachment) and it looks that in WR Switch design the oscillator starts fast enough to be stable when PLL is ready. However, it's more safe to delay reset signal in future releases of the WR Switch hardware.