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|1|Have **thermal** on all SMD pads| No thermal bridges for SMD pads on top layer. This makes soldering challenging|||
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|2|**Acute copper** on top layer and other layers| It will affect reliability||
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|3|DDR4_DQS8_x routed over split polygon|||
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|4|Tracks for decoupling capacitors are often too small| Set the track width equal to the diameter of the vias||
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|5| In L2 there is thick (2mm) P3V8 trace that connects to other layers through very tiny vias (0.3mm hole size). Increase vias dimension. [X:165mm, Y: 150mm]|||
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|6| **PMUbus**: missing connectivity to the Power Supply|Data, Clock, Control, SMBALERT signals|||
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|4|**Tracks** for decoupling capacitors are often too small| Set the track width equal to the diameter of the vias||
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|5|**Floating Cu**, unconnected trace around clocking| Should be connected to vias, leave for debugging|||
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|6| In **L2** there is thick (2mm) P3V8 trace that connects to other layers through very tiny vias (0.3mm hole size). Increase vias dimension. [X:165mm, Y: 150mm]|||
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|7| **PMUbus**: missing connectivity to the Power Supply|Data, Clock, Control, SMBALERT signals|||
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