... | ... | @@ -8,12 +8,12 @@ These documents were presented during the [New WRS-4 Workshop](https://www.ohwr. |
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| **Ports** - at least 20 ports, ideally 24 ports (HDL support) | #1, #40 | **Accepted** - prototype with 24 ports, final product TBD (min 20)|
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| **Ports** - Use compact SFP (not for DWDM) | #2 | **Rejected** - Not needed since |
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| **Ports** - It should be possible to have 1Gb on 18 ports |#3 | **Accepted** - Min support 18x1Gbps be default|
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| **Clocking circuit** - architecture |#4| **Open** - to be evaluated with a prototype|
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| **Clocking circuit** - Use PPS rising edge as reference instead of 10MHz | #6| **Accept** - HW should allow, HDL/SW to be discussed|
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|**Clocking circuit** - What should be the new WRS timing/noise performance?|#35|MDEV is limited at 5E-13/s due to flicker noise.|
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| **Ports** - WRS-v4 should have at least 20 ports, ideally 24 ports (HDL support) | #1, #40 | **Accepted** - WRS-v4 prototype with have 24 ports, final product TBD (minimum 20 ports)|
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| **Ports** - Use compact SFP (not for DWDM) | #2 | **Rejected** - Not needed, won't be used |
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| **Ports** - It should be possible to have 1Gb on 18 ports |#3 | **Accepted** - At minimum 18 x 1Gbps will be supported be default|
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| **Clocking circuit** - Architectural suggestions |#4| **Open** - to be evaluated with a prototype|
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| **Clocking circuit** - Use PPS rising edge as reference instead of 10MHz | #6| HW should allow this, HDL/SW to be discussed |
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|**Clocking circuit** - What should be the new WRS timing/noise performance?|#35|MDEV limited at 5E-13/s due to flicker noise.|
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|**Interfaces** - PPS in should be 5V TTL compatible, PPS out also TTL, always 50 ohms| #7|**Accepted**|
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|**Interfaces** - 10MHz output should be AC coupled instead of LVCMOS 3.3|#8| **Accepted** - to be tested later with measurement equipment|
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|**Interfaces** - To gain space in the front panel, squeeze the Aux/Abscal connectors|#9| Remove Aux |
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... | ... | @@ -24,25 +24,25 @@ These documents were presented during the [New WRS-4 Workshop](https://www.ohwr. |
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|**Interfaces** - Bad idea to have the button to flash directly from USB|#14|**Accepted** - do not flash from USB, remove flash button |
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|**Interfaces** - Have buttons next to LCD to change the content|#15|**Accept**|
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|**Interfaces** - LCD - overkill and takes space|#16|**Rejected** - LCD will be in the prototype, TBD for the final product|
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|**Interfaces** - SMA connector prefered|#17|**Accept**-this is our choice already|
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|**Interfaces** - SMA connector prefered|#17|**Accept** - this is our choice already|
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|**Interfaces** - UFL connector - very bad choice|#18| In the end,we will not use internal connectors, see #9|
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|**Interfaces** - External temperature sensor to know environmental conditions|#28| The front panel USB host can be used to connect temperature sensor|
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|**Interfaces** - Have USB connector inside to connect some additional sensors|#34|**Accepted** - USB host will be mounted|
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|**Interfaces** - put management ports to the right|#36|**Rejected** - Management I/F stays on the left side|
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|**Interfaces** - Put management ports to the right|#36|**Rejected** - Management I/F stays on the left side|
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|**Expansion board** - Mimic the pinout of FMC in the expansion slot|#19|**Accepted**|
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|**Expansion board **- Provide proper airflow/cooling for the expansion board|#20|**Accepted**|
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|**Expansion board** - Provide proper airflow/cooling for the expansion board|#20|**Accepted**|
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|**Expansion board** - High speed interface for data (link aggregation)|#21|**Accepted** - route to expansion board GTH/GTY links |
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|**Expansion board** - SAMTEC connector to the expansion board|#42|**Accepted** - after evaluating different options we will use SAMTEC, see (doc to be uploaded)|
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|**Memories** - Add high bandwidth external packet storage|#22|**Rejected** - we are OK with the internal memory|
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|**Memories** - A selection criteria for storage could also be TBW (TeraByte Written)|#24 #39|**Accepted** - add mSATA connector|
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|**Memories** - To speed up configuration of the FPGA one should use Dual QSPI. Is 256 MB QSPI enough?|#24|**Not an issue** Dual QSPI -> for recovery, not programming FPGA|
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|**Power supply and fans **- Power consumption of SFP+ can be 2 W|#32| **Accept** - in default config of PSU, WRS-v4 will support up to 20 ports with 2W|
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|**Power supply and fans** - emphasize that hot-swappable PSU/fan is critical/desirable|#30|**Accepted**|
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| **Power supply and fans** - consider RF-Noise and EMC when selecting PSU | #5 #31 | **Accepted** - the selected y [YH5151-1EBR](https://www.3ypower.com/en/product/1uredundant/YH5151-1EBR.html) looks good |
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|**Power supply and fans** - Power consumption of SFP+ can be 2W|#32| **Accept** - In a default HW configuration, PSU will support up to 20 ports with 2W|
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|**Power supply and fans** - Emphasize that hot-swappable PSU/fan is critical/desirable|#30|**Accepted**|
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| **Power supply and fans** - Consider RF-Noise and EMC when selecting PSU | #5 #31 | **Accepted** - the selected y [YH5151-1EBR](https://www.3ypower.com/en/product/1uredundant/YH5151-1EBR.html) looks good |
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|**Power supply and fans** - Can we make the PCB/switch fanless-ready?|#41|**Ongoing** - we will try ...|
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|**Other** - Continued supply of WR switches… - drop-in replacement|#25|**Accepted** |
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|**Other** - Filter on the inlet of airflow|#26| investigating |
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|**Other** - Dust cover unused connectors|#27|**Accepted**|
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|**Other** - Have simple version of the switch, no features, reliable → oriented for data-center|#29|This is to be considered later by companies|
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|**Other** - Dust cover for unused connectors|#27|**Accepted**|
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|**Other** - Have simple version of the switch - no features & reliable - oriented for data-center|#29|This is to be considered later by companies|
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|**Other** - N4000-13SI substrate 10 GBps?|#32| In collaboration with manufacturer selected substrate suitable for up to 25Gbps|
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|**Other** - Feedback from GSI|#38| **Accepted** - all aligned, important: non-redundant option of the WRS v4.0 | |