WR Switch gateware
Figure 1 shows the internals of the WR Switch HDL design. It contains numerous modules connected with the Wishbone Crossbar. Each of them has a Wishbone Slave interface and a number of configuration registers that are read/written from main CPU through the CPU EBI/WB bridge (WB Master interface). Blue arrows in the figure represent the WR Frabric interface connections responsible for passing Ethernet frames between the Endpoints, Switching Core and Network Interface Controller.
Fig. 1: Top HDL design of the WR Switch
Real-Time Subsystem
It contains modules responsible for the timekeeping. The components are internally connected through WB crossbar (fig. 2) and controlled from Lattice Mico 32 and main CPU (through primary WB crossbar in the top design).
Fig. 2: Internal layout of Real-Time Subsystem component
Getting Started with switch gateware (HDL) development
If you want to simulate or synthesize the WR switch gateware, have a look at the Getting started with switch gateware development wiki page.
Roadmap for gateware releases
For v3.x and v4.0 features please check previous releases wiki page.