Corrected inverted PPS output due to hardware error

ec1cf5e8 · Jesus Fernandez · 677e7ae8 · ec1cf5e8
Commit ec1cf5e8 authored Jan 13, 2022 by Jesus Fernandez
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scb_top_synthesis.vhd top/scb_18ports/scb_top_synthesis.vhd +5 -1

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--- a/top/scb_18ports/scb_top_synthesis.vhd
+++ b/top/scb_18ports/scb_top_synthesis.vhd
@@ -247,6 +247,7 @@ architecture Behavioral of scb_top_synthesis is
  signal pllout_clk_fb                          : std_logic;
  --signal pllout_dmtd_clk_fb                     : std_logic;
  signal clk_dmtd_125                           : std_logic;
+  signal pps_out                                : std_logic;

  attribute maxskew: string;
  attribute maxskew of clk_dmtd : signal is "1.0ns";
@@ -825,7 +826,7 @@ begin
      cpu_irq_n_o         => cpu_irq_n_o,
      pps_i               => pps_i,
      ppsin_term_o        => ppsin_term_o,
-      pps_o               => pps_o,
+      pps_o               => pps_out, 
      dac_helper_sync_n_o => dac_helper_sync_n_o,
      dac_helper_sclk_o   => dac_helper_sclk_o,
      dac_helper_data_o   => dac_helper_data_o,
@@ -866,6 +867,9 @@ begin
      mb_fan2_pwm_o   => mb_fan2_pwm_o,
      spll_dbg_o      => open);

+  --Reverse PPS to correct hardware mishap in physical latch
+  pps_o <= not pps_out;
+
  i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
  i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);