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White Rabbit Switch - Gateware
Commit e8328f7f authored by Maciej Lipinski's avatar Maciej Lipinski
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scb_top_sim: bugfixing and runnig top simulatio with swcore

parent 00f3e992
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Showing with 20 additions and 10 deletions
Manifest.py
View file @ e8328f7f
......@@ -3,6 +3,7 @@ modules = { "local" : [
"modules/wrsw_rt_subsystem",
"modules/wrsw_txtsu",
"modules/wrsw_swcore",
"modules/wrsw_rtu",
"platform/virtex6/chipscope",
"platform/xilinx",
"modules/softpll-new" ],
......
testbench/scb_top/main.sv
View file @ e8328f7f
......@@ -17,7 +17,7 @@ module main;
reg clk_ref=0;
reg clk_sys=0;
reg clk_mpm_core=0;
reg clk_swc_mpm_core=0;
reg rst_n=0;
parameter g_num_ports = 6;
......@@ -34,9 +34,10 @@ module main;
);
-----/\----- EXCLUDED -----/\----- */
always #5ns clk_mpm_core <=~clk_mpm_core;
always #2.5ns clk_swc_mpm_core <=~clk_swc_mpm_core;
//always #5ns clk_swc_mpm_core <=~clk_swc_mpm_core;
always #8ns clk_sys <= ~clk_sys;
always #7.998ns clk_ref <= ~clk_ref;
always #8ns clk_ref <= ~clk_ref;
// always #8ns clk_sys <= ~clk_sys;
// always #8ns clk_ref <= ~clk_ref;
......@@ -103,6 +104,7 @@ module main;
arr[j].dump();
$display("Is: ");
pkt2.dump();
$fatal("dupa"); //ML
//sfp $stop;
end
end // for (i=0;i<n_tries;i++)
......@@ -119,7 +121,7 @@ module main;
.clk_ref_i(clk_ref),
.rst_n_i(rst_n),
.cpu_irq(cpu_irq),
.clk_mpm_core_i(clk_mpm_core)
.clk_swc_mpm_core_i(clk_swc_mpm_core)
);
typedef struct {
......@@ -221,9 +223,16 @@ module main;
for(i=0;i<20;i++)
begin
$display("Try %d", i);
tx_test(seed, 20, 0, 0, ports[6].send, ports[0].recv);
tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[6].send /* src */, ports[0].recv /* sink */);
end
end
// begin
// for(i=0;i<20;i++)
// begin
// $display("Try %d", i);
// tx_test(seed /* seed */, 20 /* n_tries */, 0 /* is_q */, 0 /* unvid */, ports[5].send /* src */, ports[1].recv /* sink */);
// end
// end
forever begin
nic.update(DUT.U_Top.U_Wrapped_SCBCore.vic_irqs[0]);
@(posedge clk_sys);
......
testbench/scb_top/scb_top_sim_svwrap.svh
View file @ e8328f7f
......@@ -45,14 +45,14 @@ module scb_top_sim_svwrap
clk_ref_i,
rst_n_i,
cpu_irq,
clk_mpm_core_i
clk_swc_mpm_core_i
);
parameter g_num_ports = 6;
input clk_sys_i, clk_ref_i,rst_n_i,clk_mpm_core_i;
input clk_sys_i, clk_ref_i,rst_n_i,clk_swc_mpm_core_i;
output cpu_irq;
......@@ -260,7 +260,7 @@ scb_top_sim
.clk_ref_i ( clk_ref_i),
.clk_dmtd_i ( clk_ref_i),
.clk_sys_i ( clk_sys_i),
.clk_mpm_core_i ( clk_mpm_core_i),
.clk_swc_mpm_core_i ( clk_swc_mpm_core_i),
.wb_adr_i ( cpu.master.adr),
.wb_dat_i ( cpu.master.dat_o),
.wb_dat_o ( cpu.master.dat_i),
......
top/bare_top/scb_top_bare.vhd
View file @ e8328f7f
......@@ -515,8 +515,8 @@ begin
g_wb_ob_ignore_ack => FALSE,
g_mpm_mem_size => 65536,
g_mpm_page_size => 64,
g_mpm_ratio => 2,
g_mpm_fifo_size => 4,
g_mpm_ratio => 4, --2
g_mpm_fifo_size => 8,
g_mpm_fetch_next_pg_in_advance => FALSE
)
port map(
......
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