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White Rabbit Switch - Gateware
Commit e0a08eb7 authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore: added xswc_input block (pWB), debugging stuff, there are bugs in… 

swcore: added xswc_input block (pWB), debugging stuff, there are bugs in xswc_output (missing some words when stab/stall strange combinations
parent 7a5aeb21
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modules/wrsw_swcore/Manifest.py
View file @ e0a08eb7
...@@ -30,4 +30,5 @@ files = [ ...@@ -30,4 +30,5 @@ files = [
"swc_rr_arbiter.vhd", "swc_rr_arbiter.vhd",
"xswc_core.vhd", "xswc_core.vhd",
"xswc_output_block.vhd", "xswc_output_block.vhd",
"xswc_input_block.vhd",
] ]
\ No newline at end of file
modules/wrsw_swcore/swc_core.vhd
View file @ e0a08eb7
...@@ -62,15 +62,22 @@ entity swc_core is ...@@ -62,15 +62,22 @@ entity swc_core is
-- Fabric I/F : input (comes from the Endpoint) -- Fabric I/F : input (comes from the Endpoint)
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
tx_sof_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_sof_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_eof_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_eof_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_data_i : in std_logic_vector(c_swc_num_ports * c_swc_data_width - 1 downto 0); -- tx_data_i : in std_logic_vector(c_swc_num_ports * c_swc_data_width - 1 downto 0);
tx_ctrl_i : in std_logic_vector(c_swc_num_ports * c_swc_ctrl_width - 1 downto 0); -- tx_ctrl_i : in std_logic_vector(c_swc_num_ports * c_swc_ctrl_width - 1 downto 0);
tx_valid_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_valid_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_bytesel_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_bytesel_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_dreq_o : out std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_dreq_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_abort_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_abort_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_rerror_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_rerror_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
-------------------------------------------------------------------------------
-- pWB : input (comes from the Endpoint)
-------------------------------------------------------------------------------
snk_i : in t_wrf_sink_in_array(g_swc_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_swc_num_ports-1 downto 0);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Fabric I/F : output (goes to the Endpoint) -- Fabric I/F : output (goes to the Endpoint)
...@@ -259,22 +266,27 @@ architecture rtl of swc_core is ...@@ -259,22 +266,27 @@ architecture rtl of swc_core is
gen_blocks : for i in 0 to c_swc_num_ports-1 generate gen_blocks : for i in 0 to c_swc_num_ports-1 generate
INPUT_BLOCK : swc_input_block INPUT_BLOCK : xswc_input_block
port map ( port map (
clk_i => clk_i, clk_i => clk_i,
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Fabric I/F -- Fabric I/F
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
tx_sof_p1_i => tx_sof_p1_i(i), -- tx_sof_p1_i => tx_sof_p1_i(i),
tx_eof_p1_i => tx_eof_p1_i(i), -- tx_eof_p1_i => tx_eof_p1_i(i),
tx_data_i => tx_data_i ((i + 1) * c_swc_data_width -1 downto i * c_swc_data_width), -- tx_data_i => tx_data_i ((i + 1) * c_swc_data_width -1 downto i * c_swc_data_width),
tx_ctrl_i => tx_ctrl_i((i + 1) * c_swc_ctrl_width -1 downto i * c_swc_ctrl_width), -- tx_ctrl_i => tx_ctrl_i((i + 1) * c_swc_ctrl_width -1 downto i * c_swc_ctrl_width),
tx_valid_i => tx_valid_i(i), -- tx_valid_i => tx_valid_i(i),
tx_bytesel_i => tx_bytesel_i(i), -- tx_bytesel_i => tx_bytesel_i(i),
tx_dreq_o => tx_dreq_o(i), -- tx_dreq_o => tx_dreq_o(i),
tx_abort_p1_i => tx_abort_p1_i(i), -- tx_abort_p1_i => tx_abort_p1_i(i),
tx_rerror_p1_i => tx_rerror_p1_i(i), -- tx_rerror_p1_i => tx_rerror_p1_i(i),
-------------------------------------------------------------------------------
-- pWB : input (comes from the Endpoint)
-------------------------------------------------------------------------------
snk_i => snk_i(i),
snk_o => snk_o(i),
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- I/F with Page allocator (MMU) -- I/F with Page allocator (MMU)
......
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ e0a08eb7
...@@ -291,7 +291,63 @@ package swc_swcore_pkg is ...@@ -291,7 +291,63 @@ package swc_swcore_pkg is
); );
end component; end component;
component xswc_input_block is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- pWB : input (comes from the Endpoint)
-------------------------------------------------------------------------------
snk_i : in t_wrf_sink_in;
snk_o : out t_wrf_sink_out;
-------------------------------------------------------------------------------
-- I/F with Page allocator (MMU)
-------------------------------------------------------------------------------
mmu_page_alloc_req_o : out std_logic;
mmu_page_alloc_done_i : in std_logic;
mmu_pageaddr_i : in std_logic_vector(c_swc_page_addr_width - 1 downto 0);
mmu_pageaddr_o : out std_logic_vector(c_swc_page_addr_width - 1 downto 0);
mmu_force_free_o : out std_logic;
mmu_force_free_done_i : in std_logic;
mmu_force_free_addr_o : out std_logic_vector(c_swc_page_addr_width - 1 downto 0);
mmu_set_usecnt_o : out std_logic;
mmu_set_usecnt_done_i : in std_logic;
mmu_usecnt_o : out std_logic_vector(c_swc_usecount_width - 1 downto 0);
mmu_nomem_i : in std_logic;
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
rtu_rsp_valid_i : in std_logic;
rtu_rsp_ack_o : out std_logic;
rtu_dst_port_mask_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
rtu_drop_i : in std_logic;
rtu_prio_i : in std_logic_vector(c_swc_prio_width - 1 downto 0);
-------------------------------------------------------------------------------
-- I/F with Multiport Memory (MPU)
-------------------------------------------------------------------------------
mpm_pckstart_o : out std_logic;
mpm_pageaddr_o : out std_logic_vector(c_swc_page_addr_width - 1 downto 0);
mpm_pagereq_o : out std_logic;
mpm_pageend_i : in std_logic;
mpm_data_o : out std_logic_vector(c_swc_data_width - 1 downto 0);
mpm_ctrl_o : out std_logic_vector(c_swc_ctrl_width - 1 downto 0);
mpm_drdy_o : out std_logic;
mpm_full_i : in std_logic;
mpm_flush_o : out std_logic;
mpm_wr_sync_i : in std_logic;
-------------------------------------------------------------------------------
-- I/F with Page Transfer Arbiter (PTA)
-------------------------------------------------------------------------------
pta_transfer_pck_o : out std_logic;
pta_transfer_ack_i : in std_logic;
pta_pageaddr_o : out std_logic_vector(c_swc_page_addr_width - 1 downto 0);
pta_mask_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
pta_pck_size_o : out std_logic_vector(c_swc_max_pck_size_width - 1 downto 0);
pta_prio_o : out std_logic_vector(c_swc_prio_width - 1 downto 0)
);
end component;
component swc_multiport_page_allocator is component swc_multiport_page_allocator is
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
......
modules/wrsw_swcore/xswc_core.vhd
View file @ e0a08eb7
...@@ -101,15 +101,22 @@ architecture rtl of xswc_core is ...@@ -101,15 +101,22 @@ architecture rtl of xswc_core is
-- Fabric I/F : input (comes from the Endpoint) -- Fabric I/F : input (comes from the Endpoint)
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
tx_sof_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_sof_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_eof_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_eof_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_data_i : in std_logic_vector(c_swc_num_ports * c_swc_data_width - 1 downto 0); -- tx_data_i : in std_logic_vector(c_swc_num_ports * c_swc_data_width - 1 downto 0);
tx_ctrl_i : in std_logic_vector(c_swc_num_ports * c_swc_ctrl_width - 1 downto 0); -- tx_ctrl_i : in std_logic_vector(c_swc_num_ports * c_swc_ctrl_width - 1 downto 0);
tx_valid_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_valid_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_bytesel_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_bytesel_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_dreq_o : out std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_dreq_o : out std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_abort_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_abort_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
tx_rerror_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0); -- tx_rerror_p1_i : in std_logic_vector(c_swc_num_ports - 1 downto 0);
-------------------------------------------------------------------------------
-- pWB : input (comes from the Endpoint)
-------------------------------------------------------------------------------
snk_i : in t_wrf_sink_in_array(g_swc_num_ports-1 downto 0);
snk_o : out t_wrf_sink_out_array(g_swc_num_ports-1 downto 0);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Fabric I/F : output (goes to the Endpoint) -- Fabric I/F : output (goes to the Endpoint)
...@@ -194,17 +201,17 @@ architecture rtl of xswc_core is ...@@ -194,17 +201,17 @@ architecture rtl of xswc_core is
end component ; end component ;
signal swc_snk_sof_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0); -- signal swc_snk_sof_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal swc_snk_eof_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0); -- signal swc_snk_eof_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal swc_snk_dreq : std_logic_vector(c_swc_num_ports - 1 downto 0); -- signal swc_snk_dreq : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal swc_snk_ctrl : std_logic_vector(c_swc_num_ports * c_swc_ctrl_width - 1 downto 0); -- signal swc_snk_ctrl : std_logic_vector(c_swc_num_ports * c_swc_ctrl_width - 1 downto 0);
signal swc_snk_data : std_logic_vector(c_swc_num_ports * c_swc_data_width - 1 downto 0); -- signal swc_snk_data : std_logic_vector(c_swc_num_ports * c_swc_data_width - 1 downto 0);
signal swc_snk_valid : std_logic_vector(c_swc_num_ports - 1 downto 0); -- signal swc_snk_valid : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal swc_snk_bytesel : std_logic_vector(c_swc_num_ports - 1 downto 0); -- signal swc_snk_bytesel : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal swc_snk_idle : std_logic_vector(c_swc_num_ports - 1 downto 0); -- signal swc_snk_idle : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal swc_snk_rerror_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0); -- signal swc_snk_rerror_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal swc_snk_terror_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0); -- signal swc_snk_terror_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal swc_snk_tabort_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0); -- signal swc_snk_tabort_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0);
-- signal swc_src_sof_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0); -- signal swc_src_sof_p1 : std_logic_vector(c_swc_num_ports - 1 downto 0);
...@@ -223,26 +230,26 @@ begin ...@@ -223,26 +230,26 @@ begin
gen_port_connections : for i in 0 to g_swc_num_ports-1 generate -- gen_port_connections : for i in 0 to g_swc_num_ports-1 generate
swc_snk_ctrl((i+1)*c_swc_ctrl_width - 1 downto i*c_swc_ctrl_width + 2) <= (others => '0'); -- swc_snk_ctrl((i+1)*c_swc_ctrl_width - 1 downto i*c_swc_ctrl_width + 2) <= (others => '0');
CONV_wb_to_wrf: xwb_fabric_sink -- CONV_wb_to_wrf: xwb_fabric_sink
--
port map( -- port map(
clk_i => clk_i, -- clk_i => clk_i,
rst_n_i => rst_n_i, -- rst_n_i => rst_n_i,
snk_i => snk_i(i), -- snk_i => snk_i(i),
snk_o => snk_o(i), -- snk_o => snk_o(i),
addr_o => swc_snk_ctrl((i+1)*c_swc_ctrl_width - 3 downto i*c_swc_ctrl_width), -- addr_o => swc_snk_ctrl((i+1)*c_swc_ctrl_width - 3 downto i*c_swc_ctrl_width),
data_o => swc_snk_data((i+1)*c_swc_data_width - 1 downto i*c_swc_data_width), -- data_o => swc_snk_data((i+1)*c_swc_data_width - 1 downto i*c_swc_data_width),
dvalid_o => swc_snk_valid(i), -- dvalid_o => swc_snk_valid(i),
sof_o => swc_snk_sof_p1(i), -- sof_o => swc_snk_sof_p1(i),
eof_o => swc_snk_eof_p1(i), -- eof_o => swc_snk_eof_p1(i),
error_o => swc_snk_rerror_p1(i), -- error_o => swc_snk_rerror_p1(i),
bytesel_o => swc_snk_bytesel(i), -- bytesel_o => swc_snk_bytesel(i),
dreq_i => swc_snk_dreq(i) -- dreq_i => swc_snk_dreq(i)
); -- );
-- CONV_wrf_to_wb: xwb_fabric_source -- CONV_wrf_to_wb: xwb_fabric_source
-- --
...@@ -261,9 +268,9 @@ begin ...@@ -261,9 +268,9 @@ begin
-- dreq_o => swc_src_dreq(i) -- dreq_o => swc_src_dreq(i)
-- ); -- );
end generate; -- end generate;
swc_snk_tabort_p1 <= (others => '0'); -- swc_snk_tabort_p1 <= (others => '0');
-- swc_src_terror_p1 <= (others => '0'); -- swc_src_terror_p1 <= (others => '0');
-- swc_src_tabort_p1 <= (others => '0'); -- swc_src_tabort_p1 <= (others => '0');
...@@ -274,16 +281,19 @@ begin ...@@ -274,16 +281,19 @@ begin
rst_n_i => rst_n_i, rst_n_i => rst_n_i,
-- this is swc_sink (input data) -- this is swc_sink (input data)
tx_sof_p1_i => swc_snk_sof_p1, -- tx_sof_p1_i => swc_snk_sof_p1,
tx_eof_p1_i => swc_snk_eof_p1, -- tx_eof_p1_i => swc_snk_eof_p1,
tx_data_i => swc_snk_data, -- tx_data_i => swc_snk_data,
tx_ctrl_i => swc_snk_ctrl, -- tx_ctrl_i => swc_snk_ctrl,
tx_valid_i => swc_snk_valid, -- tx_valid_i => swc_snk_valid,
tx_bytesel_i => swc_snk_bytesel, -- tx_bytesel_i => swc_snk_bytesel,
tx_dreq_o => swc_snk_dreq, -- tx_dreq_o => swc_snk_dreq,
tx_abort_p1_i => swc_snk_tabort_p1, -- fake -- tx_abort_p1_i => swc_snk_tabort_p1, -- fake
tx_rerror_p1_i => swc_snk_rerror_p1, -- tx_rerror_p1_i => swc_snk_rerror_p1,
snk_i => snk_i,
snk_o => snk_o,
--this is swc_source (itput data) --this is swc_source (itput data)
-- rx_sof_p1_o => swc_src_sof_p1, -- rx_sof_p1_o => swc_src_sof_p1,
-- rx_eof_p1_o => swc_src_eof_p1, -- rx_eof_p1_o => swc_src_eof_p1,
......
modules/wrsw_swcore/xswc_input_block.vhd 0 → 100644
View file @ e0a08eb7
This diff is collapsed.
modules/wrsw_swcore/xswc_output_block.vhd
View file @ e0a08eb7
...@@ -174,10 +174,15 @@ architecture behavoural of xswc_output_block is ...@@ -174,10 +174,15 @@ architecture behavoural of xswc_output_block is
signal src_err_int : std_logic; signal src_err_int : std_logic;
signal src_rty_int : std_logic; signal src_rty_int : std_logic;
signal mpm_data : std_logic_vector(c_swc_data_width + c_swc_ctrl_width - 1 downto 0); signal snk_ack_count : unsigned(2 downto 0); -- size?
signal snk_ack_count : unsigned(2 downto 0); -- size?
signal src_stall_d0 : std_logic; signal src_stall_d0 : std_logic;
signal mpm_drdy_d0 : std_logic;
signal special_dreq : std_logic;
signal special_dreq_d0 : std_logic;
begin -- behavoural begin -- behavoural
...@@ -318,7 +323,7 @@ begin -- behavoural ...@@ -318,7 +323,7 @@ begin -- behavoural
cnt_last_word <= '0'; cnt_last_word <= '0';
cnt_pck_size <= (others => '0'); cnt_pck_size <= (others => '0');
cnt_pck_size(0) <= '1'; -- cnt_pck_size(0) <= '1';
cnt_one_but_last_word <= '0'; cnt_one_but_last_word <= '0';
else else
...@@ -328,6 +333,7 @@ begin -- behavoural ...@@ -328,6 +333,7 @@ begin -- behavoural
if(state = SET_PAGE) then if(state = SET_PAGE) then
cnt_pck_size <= (others =>'0'); cnt_pck_size <= (others =>'0');
-- cnt_pck_size(0) <= '1';
cnt_one_but_last_word <= '0'; cnt_one_but_last_word <= '0';
cnt_last_word <= '0'; cnt_last_word <= '0';
...@@ -377,15 +383,20 @@ begin -- behavoural ...@@ -377,15 +383,20 @@ begin -- behavoural
current_pck_size <= (others => '0'); current_pck_size <= (others => '0');
pck_start_pgaddr <= (others => '0'); pck_start_pgaddr <= (others => '0');
dreq <= '0'; dreq <= '0';
special_dreq <= '0';
special_dreq_d0 <= '0';
waiting_pck_start <= '0'; waiting_pck_start <= '0';
mpm_drdy_d0 <= '0';
else else
-------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------
-- some helpers to the state machines -- some helpers to the state machines
-------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------
src_stall_d0 <= src_stall_int; src_stall_d0 <= src_stall_int;
special_dreq_d0 <= special_dreq;
mpm_drdy_d0 <= mpm_drdy_i;
-- traccking ACKs from the sink -- traccking ACKs from the sink
if (src_cyc_int = '0' or src_err_int = '1') then if (src_cyc_int = '0' or src_err_int = '1') then
...@@ -424,7 +435,7 @@ begin -- behavoural ...@@ -424,7 +435,7 @@ begin -- behavoural
start_free_pck <= '0'; start_free_pck <= '0';
pgreq <= '0'; pgreq <= '0';
dreq <= '0'; dreq <= '0';
special_dreq <= '0';
waiting_pck_start <= '0'; waiting_pck_start <= '0';
if(rd_data_valid = '1' and src_stall_int = '0' and src_err_int ='0') then if(rd_data_valid = '1' and src_stall_int = '0' and src_err_int ='0') then
...@@ -471,23 +482,33 @@ begin -- behavoural ...@@ -471,23 +482,33 @@ begin -- behavoural
else -- everything works else -- everything works
dreq <= '1'; -- enable stall-to-dreq translation dreq <= '1'; -- enable stall-to-dreq translation
special_dreq <= '0';
if(mpm_drdy_i = '0') then -- paused by source if(mpm_drdy_i = '0' ) then -- paused by source
src_cyc_int <= '1'; src_cyc_int <= '1';
src_stb_int <= '0'; src_stb_int <= '0';
elsif(mpm_drdy_i = '1' and src_stall_int = '1') then -- paused by sink elsif(mpm_drdy_i = '1' and src_stall_int = '1') then -- paused by sink
src_cyc_tmp <= '1'; src_cyc_tmp <= '1';
src_stb_tmp <= '1'; src_stb_tmp <= '1';
src_adr_tmp <= mpm_data(17 downto 16);
src_dat_tmp <= mpm_data(15 downto 0); if(src_stb_int = '1') then -- when stall is after drdy_i LOW
src_sel_tmp <= '1' & not mpm_ctrl_i(3); src_adr_tmp <= mpm_ctrl_i(1 downto 0);
src_sel_tmp <= mpm_ctrl_i(3 downto 2);
src_dat_tmp <= mpm_data_i;
else
src_adr_int <= mpm_ctrl_i(1 downto 0);
src_sel_int <= mpm_ctrl_i(3 downto 2);
src_dat_int <= mpm_data_i;
end if;
elsif(mpm_drdy_i = '1' and src_stall_int = '0') then -- read data elsif(mpm_drdy_i = '1' and src_stall_int = '0') then -- read data
if(src_stall_d0 = '1') then -- read stored data in tmp reg if(src_stall_d0 = '1') then -- read stored data in tmp reg
-- (stopped by source before) -- (stopped by source before)
src_adr_int <= src_adr_tmp; src_adr_int <= src_adr_tmp;
src_dat_int <= src_dat_tmp; src_dat_int <= src_dat_tmp;
...@@ -495,14 +516,22 @@ begin -- behavoural ...@@ -495,14 +516,22 @@ begin -- behavoural
else -- normal read else -- normal read
src_adr_int <= mpm_data(17 downto 16); src_adr_int <= mpm_ctrl_i(1 downto 0);
src_dat_int <= mpm_data(15 downto 0); src_sel_int <= mpm_ctrl_i(3 downto 2);
src_sel_int <= '1' & not mpm_ctrl_i(3); src_dat_int <= mpm_data_i;
end if; end if;
-- if(cnt_one_but_last_word = '1') then -- this was the last word of the
if(cnt_last_word = '1') then -- this was the last word of the if(cnt_last_word = '1') then -- this was the last word of the
state <= READ_LAST_WORD; -- frame (package) state <= READ_LAST_WORD; -- frame (package)
-- if(src_stall_int = '0') then
-- src_stb_int <= '0';
-- end if;
end if; end if;
end if; --if(mpm_drdy_i = '0') then end if; --if(mpm_drdy_i = '0') then
...@@ -558,7 +587,7 @@ begin -- behavoural ...@@ -558,7 +587,7 @@ begin -- behavoural
rd_pck_size <= rd_data(c_swc_max_pck_size_width + c_swc_page_addr_width - 1 downto c_swc_page_addr_width); rd_pck_size <= rd_data(c_swc_max_pck_size_width + c_swc_page_addr_width - 1 downto c_swc_page_addr_width);
-------------- MPM --------------------- -------------- MPM ---------------------
mpm_dreq_o <= (not src_stall_int) and dreq; mpm_dreq_o <= ((not src_stall_int) and dreq);
mpm_pgreq_o <= pgreq; mpm_pgreq_o <= pgreq;
mpm_pgaddr_o <= rd_data(c_swc_page_addr_width - 1 downto 0) when (pgreq = '1') else pck_start_pgaddr; mpm_pgaddr_o <= rd_data(c_swc_page_addr_width - 1 downto 0) when (pgreq = '1') else pck_start_pgaddr;
-------------- pWB ---------------------- -------------- pWB ----------------------
...@@ -577,8 +606,5 @@ begin -- behavoural ...@@ -577,8 +606,5 @@ begin -- behavoural
-------------- PPFM ---------------------- -------------- PPFM ----------------------
ppfm_free_o <= ppfm_free; ppfm_free_o <= ppfm_free;
ppfm_free_pgaddr_o <= ppfm_free_pgaddr; ppfm_free_pgaddr_o <= ppfm_free_pgaddr;
---- tmp
mpm_data <= mpm_ctrl_i & mpm_data_i;
end behavoural; end behavoural;
\ No newline at end of file
testbench/swcore/xswc_core.sv
View file @ e0a08eb7
...@@ -195,6 +195,8 @@ module main; ...@@ -195,6 +195,8 @@ module main;
gen.set_size(46, 1000); gen.set_size(46, 1000);
pkt = gen.gen(); pkt = gen.gen();
//pkt.set_size(100);
q.push_back(pkt); q.push_back(pkt);
set_rtu_rsp(port,1,drop /*drop*/,prio /*prio*/,mask /*mask*/); set_rtu_rsp(port,1,drop /*drop*/,prio /*prio*/,mask /*mask*/);
......
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