v4-dev and v3.3 merge

dc10a88b · Maciej Lipinski · bd219537 · 64d2e213 · 54278b11 · dc10a88b
Commit dc10a88b authored Apr 29, 2013 by Maciej Lipinski
11 changed files
--- a/wr-cores @ 54278b11
+++ b/wr-cores @ 54278b11
-Subproject commit 5bc1aa29ffdeff2aa3dc0f5ac9263d5b53c0313f
+Subproject commit 54278b11af08768c4f60905e94e09d1de406e3a5
--- a/modules/wrsw_rtu/rtu_lookup_engine.vhd
+++ b/modules/wrsw_rtu/rtu_lookup_engine.vhd
@@ -6,7 +6,7 @@
 -- Author     : Maciej Lipinski
 -- Company    : CERN BE-Co-HT
 -- Created    : 2010-05-22
-- Last update: 2012-06-28
+-- Last update: 2013-03-24
 -- Platform   : FPGA-generic
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -35,6 +35,7 @@
 -- Revisions  :
 -- Date        Version  Author          Description
 -- 2010-05-22  1.0      lipinskimm          Created
+-- 2013-03-24  1.1      lipinskimm          aging-related bugfix
 -------------------------------------------------------------------------------


@@ -49,6 +50,7 @@ use work.genram_pkg.all;

 entity rtu_lookup_engine is
  generic(
+    g_num_ports : integer;
    g_hash_size : integer := 11);
  port(

@@ -90,6 +92,14 @@ entity rtu_lookup_engine is
    -- indicates that the search has been finished (whether the entry was found or not)
    drdy_o  : out std_logic;

+    -- mask indicating the source of request (on which port the frame was received)
+    port_i : in std_logic_vector(g_num_ports -1 downto 0); -- ML (24/03/2013): aging bugfix
+    
+    -- indicates whetehr the sarch concenrs
+    -- 0: source MAC
+    -- 1: destination MAC
+    src_dst_i : in std_logic; -- ML (24/03/2013): aging bugfix
+
    -------------------------------------------------------------------------------
    -- read data
    -------------------------------------------------------------------------------  
@@ -220,11 +230,22 @@ begin
          when NEXT_BUCKET =>

            -- got a match?
-            if(cur_entry.valid = '1' and cur_entry.fid = fid_i and cur_entry.mac = mac_i) then
+            -- ML (24/03/2013): aging bugfix --------------------------------------------------
+            if(cur_entry.valid = '1' and cur_entry.fid = fid_i and cur_entry.mac = mac_i and 
+               src_dst_i = '0' and -- this is source MAC => need to check that it's been received
+                                   -- on the correct port:
+               (cur_entry.port_mask_dst(g_num_ports-1 downto 0) and port_i) = port_i)  then
+              drdy_o       <= '1';
+              found_o      <= '1';
+              entry_o      <= cur_entry;
+              lookup_state <= OUTPUT_RESULT;
+            elsif(cur_entry.valid = '1' and cur_entry.fid = fid_i and cur_entry.mac = mac_i and 
+                  src_dst_i = '1')  then  -- this is destination MAC search, 
              drdy_o       <= '1';
              found_o      <= '1';
              entry_o      <= cur_entry;
              lookup_state <= OUTPUT_RESULT;
+            ------------------------------------------------------------------------------------
            elsif(bucket_entry = "00" or cur_entry.valid = '0') then
              drdy_o       <= '1';
              found_o      <= '0';

--- a/modules/wrsw_rtu/rtu_match.vhd
+++ b/modules/wrsw_rtu/rtu_match.vhd
@@ -40,6 +40,10 @@
 -- Date        Version  Author          Description
 -- 2010-05-08  1.0      lipinskimm          Created
 -- 2010-05-22  1.1      lipinskimm          revised, developed further
+-- 2013-03-24  1.2      mlipinsk            aging bugfix: don't update aram when DST_MAC found
+-- 2013-04-12  1.3      mlipinsk            1. no ureq for unrecognized destination MAC
+--                                          2. pass_bpdu overrides only pass_all = FALSE
+--                                          3. entering LEARN_SRC only for SRC_MAC search
 -------------------------------------------------------------------------------
 -------------------------------------------------------------------------------

@@ -98,6 +102,8 @@ entity rtu_match is
    htab_fid_o   : out std_logic_vector(c_wrsw_fid_width - 1 downto 0);
    htab_drdy_i  : in  std_logic;
    htab_entry_i : in  t_rtu_htab_entry;
+    htab_port_o  : out std_logic_vector(g_num_ports-1 downto 0); -- ML (24/03/2013): aging bugfix
+    htab_src_dst_o:out std_logic;                                -- ML (24/03/2013): aging bugfix

    -------------------------------------------------------------------------------
    -- Unrecongized FIFO (operated by WB)
@@ -336,6 +342,7 @@ architecture behavioral of rtu_match is

  signal requesting_port       : std_logic_vector(g_num_ports-1 downto 0);
  signal s_urec_broadcast_mask : std_logic_vector(c_RTU_MAX_PORTS-1 downto 0);  
+  signal zeros : std_logic_vector(g_num_ports-1 downto 0);
 -------------------------------------------------------------------------------------------------------------------------
 --| Address outs and flag generation and 
 -------------------------------------------------------------------------------------------------------------------------
@@ -352,8 +359,16 @@ begin

  -- if forward of unrecognized frames to CPU is disabled (LOW), then we use
  -- the cpu_mask to forward everywhere but to CPU, otherwise we do on all ports
-  s_urec_broadcast_mask <= (not rtu_cpu_mask_i) when (rtu_b_unrec_fw_cpu_i = '0') else
-                           (others =>'1');
+--   s_urec_broadcast_mask <= (not rtu_cpu_mask_i) when (rtu_b_unrec_fw_cpu_i = '0') else
+--                            (others =>'1');
+
+  -- ML (11/04/2013) : to prevent broadcasting of unrecognized frames to CPU
+  s_urec_broadcast_mask(g_num_ports-1     downto 0)           <= (others =>'1');
+  s_urec_broadcast_mask(c_RTU_MAX_PORTS-1 downto g_num_ports) <= (others =>'1') when (rtu_b_unrec_fw_cpu_i = '1') 
+                                                                 (others =>'0');   
+
+  zeros <= (others =>'0');
+
  -----------------------------------------------------------------------------------------------------------------------
  --| Hash calculation
  -----------------------------------------------------------------------------------------------------------------------
@@ -686,18 +701,17 @@ begin
              -------------------------------------------
              if(htab_found_i = '1') then

-                -- update aging aram (in any case that entry was found,
-                -- even if dropped later, we update aging aram
-                s_aram_main_data_o <= rtu_aram_main_data_i or f_onehot_encode(to_integer(unsigned(std_logic_vector'(s_aram_bitsel_msb & htab_entry_i.bucket_entry))), 32);
-                -- strange hack do to t_mac_array of std_logic_vector declaration
-                -- solution taken from :http://www.velocityreviews.com/forums/t639905-ambiguous-type-in-infix-expression.html
-                s_aram_main_wr     <= '1';
-
                ----------------------------------------------------------------------------
                --  SOURCE MAC ENTRY SEARCH 
                ----------------------------------------------------------------------------                      
                if(s_src_dst_sel = '0') then

+                  -- ML (24/03/2013): aging bugfix : update aging only for source found
+                  -- update aging aram (in any case that entry was found,
+                  -- even if dropped later, we update aging aram
+                  s_aram_main_data_o <= rtu_aram_main_data_i or f_onehot_encode(to_integer(unsigned(s_aram_bitsel_msb & htab_entry_i.bucket_entry)), 32);
+                  s_aram_main_wr     <= '1';
+
                  -------------------------------------------       
                  -- source MAC address is blocked? - 
                  -- drop the package
@@ -817,7 +831,8 @@ begin
                    ----------------------------------------------------------------------------                      
                  else
                    
-                    s_dst_entry_port_mask_dst <= s_urec_broadcast_mask; --ML changed (mar2013) to avoid broadcast to NIC, old:(others => '1');
+--                     s_dst_entry_port_mask_dst <= (others => '1');
+                    s_dst_entry_port_mask_dst <= s_urec_broadcast_mask; -- ML(11/04/2013)
                    s_dst_entry_is_bpdu       <= '0';  -- changed
                  end if;  -- if( s_src_dst_sel = '0') then            

@@ -826,7 +841,11 @@ begin
                  -- learning fifo, and we have not yet
                  -- stored info about this request
                  -------------------------------------------
-                  if((rtu_ufifo_wr_full_i = '0') and (s_rtu_pcr_learn_en = '1') and (s_rq_learned_reg = '0')) then
+                  if((rtu_ufifo_wr_full_i = '0') and (s_rtu_pcr_learn_en = '1') and (s_rq_learned_reg = '0')
+                      -- ML 24/03/2013: we don't need to make unrecongized request 
+                      -- for destination unrecognized MAC - we have no idea 
+                      -- where to forward it anyway
+                     and s_src_dst_sel = '0') then

                    mstate             <= LEARN_SRC;
                    s_rtu_ufifo_wr_req <= '1';
@@ -906,7 +925,8 @@ begin
                -- so we broardcast
                
                s_dst_entry_is_bpdu       <= '0';
-                s_dst_entry_port_mask_dst <= s_urec_broadcast_mask; --ML changed (mar2013) to avoid broadcast to NIC, old: (others => '1');
+--                 s_dst_entry_port_mask_dst <= (others => '1');
+                s_dst_entry_port_mask_dst <= s_urec_broadcast_mask; -- ML(11/04/2013)

                -------------------------------------------       
                -- not broadcast unrecognized requests = drop
@@ -988,8 +1008,9 @@ begin
                  else
                    
                    s_dst_entry_is_bpdu       <= '0';
-                    s_dst_entry_port_mask_dst <= s_urec_broadcast_mask; --ML changed (mar2013) to avoid broadcast to NIC, old:(others => '1');
-                    
+--                     s_dst_entry_port_mask_dst <= (others => '1');
+                    s_dst_entry_port_mask_dst <= s_urec_broadcast_mask; -- ML(11/04/2013)
+                                        
                  end if;


@@ -1059,7 +1080,12 @@ begin
              --  if we are in pass_bpdu, and the dst
              -- entry is not bpdu, drop  
              -------------------------------------------    
-              if((s_rtu_pcr_pass_bpdu = '1') and (s_dst_entry_is_bpdu = '0')) then
+              if((s_rtu_pcr_pass_bpdu = '1') and (s_dst_entry_is_bpdu = '0') 
+                 --ML(12/04/2013): change to make sure that we drop non-bpdu frames
+                 --only when pass_all=FALSE (before, it was necessary to change to TRUE
+                 --both, pass_bpdu and pass_all, to enable normal (non-bpdu) traffic
+                 --on a port
+                 and ((requesting_port and rtu_pcr_pass_all_i) = zeros)) then 

                -- RETURN
                s_rsp_drop          <= '1';
@@ -1192,5 +1218,8 @@ begin

 rsp_fifo_output_o <= s_rsp_bpdu & s_rsp_dst_port_mask & s_rsp_drop & s_rsp_prio & s_port_id;

+  htab_src_dst_o <= s_src_dst_sel; -- ML (24/03/2013): aging bugfix
+  htab_port_o    <= s_port_id;     -- ML (24/03/2013): aging bugfix
+  
 end architecture;

--- a/modules/wrsw_rtu/rtu_private_pkg.vhd
+++ b/modules/wrsw_rtu/rtu_private_pkg.vhd
@@ -337,6 +337,7 @@ package rtu_private_pkg is

  component rtu_lookup_engine
    generic (
+      g_num_ports : integer;
      g_hash_size : integer := c_wrsw_hash_width);
    port (
      clk_match_i      : in  std_logic;
@@ -355,6 +356,8 @@ package rtu_private_pkg is
      mac_i            : in  std_logic_vector(c_wrsw_mac_addr_width -1 downto 0);
      fid_i            : in  std_logic_vector(c_wrsw_fid_width - 1 downto 0);
      drdy_o           : out std_logic;
+      port_i           : in std_logic_vector(g_num_ports -1 downto 0); -- ML (24/03/2013): aging bugfix
+      src_dst_i        : in std_logic;                                 -- ML (24/03/2013): aging bugfix
      entry_o          : out t_rtu_htab_entry);
  end component;

@@ -390,6 +393,8 @@ package rtu_private_pkg is
      htab_fid_o           : out std_logic_vector(c_wrsw_fid_width - 1 downto 0);
      htab_drdy_i          : in  std_logic;
      htab_entry_i         : in  t_rtu_htab_entry;
+      htab_port_o          : out std_logic_vector(g_num_ports-1 downto 0); -- ML (24/03/2013): aging bugfix
+      htab_src_dst_o       : out std_logic;                                -- ML (24/03/2013): aging bugfix
      rtu_ufifo_wr_req_o   : out std_logic;
      rtu_ufifo_wr_full_i  : in  std_logic;
      rtu_ufifo_wr_empty_i : in  std_logic;

--- a/modules/wrsw_rtu/wrsw_rtu.vhd
+++ b/modules/wrsw_rtu/wrsw_rtu.vhd
@@ -337,6 +337,9 @@ architecture behavioral of wrsw_rtu is

  signal current_pcr : integer;

+  signal htab_port : std_logic_vector(g_num_ports - 1 downto 0);
+  signal htab_src_dst : std_logic;
+  
  function f_slice (
    x     : std_logic_vector;
    index : integer;
@@ -504,6 +507,8 @@ begin
      htab_fid_o   => htab_fid,
      htab_drdy_i  => htab_drdy,
      htab_entry_i => htab_entry,
+      htab_port_o    => htab_port,    -- ML (24/03/2013): aging bugfix
+      htab_src_dst_o => htab_src_dst, -- ML (24/03/2013): aging bugfix

      rtu_ufifo_wr_req_o   => regs_towb.ufifo_wr_req_i,
      rtu_ufifo_wr_full_i  => regs_fromwb.ufifo_wr_full_o,
@@ -541,6 +546,8 @@ begin
  mfifo_trigger <= regs_fromwb.gcr_mfifotrig_o and regs_fromwb.gcr_mfifotrig_load_o;

  U_Lookup : rtu_lookup_engine
+    generic map (
+      g_num_ports => g_num_ports)
    port map (
      clk_sys_i   => clk_sys_i,
      clk_match_i => clk_sys_i,
@@ -560,6 +567,8 @@ begin
      mac_i   => htab_mac,
      fid_i   => htab_fid,
      drdy_o  => htab_drdy,
+      port_i  => htab_port,      -- ML (24/03/2013): aging bugfix
+      src_dst_i => htab_src_dst, -- ML (24/03/2013): aging bugfix
      entry_o => htab_entry
      );


--- a/syn/scb_8ports/test_scb.xise
+++ b/syn/scb_8ports/test_scb.xise
 <?xml version="1.0" ?>
 <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
 	<header>
 		<!-- ISE source project file created by Project Navigator.             -->
 		<!--                                                                   -->
@@ -1119,4 +1120,5 @@
 </files>
 	<bindings/>
 	<version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
+
 </project>
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -90,16 +90,16 @@ entity scb_top_bare is
    -------------------------------------------------------------------------------

    -- GTX clock fanout enable
-    clk_en_o  : out std_logic;
+    clk_en_o : out std_logic;

    -- GTX clock fanout source select
    clk_sel_o : out std_logic;

    -- DMTD clock divider selection (0 = 125 MHz, 1 = 62.5 MHz)
-    clk_dmtd_divsel_o: out std_logic;
+    clk_dmtd_divsel_o : out std_logic;

    -- UART source selection (FPGA/DBGU)
-    uart_sel_o: out std_logic;
+    uart_sel_o : out std_logic;

    ---------------------------------------------------------------------------
    -- GTX ports
@@ -125,13 +125,20 @@ entity scb_top_bare is
    i2c_scl_i     : in  std_logic_vector(2 downto 0) := "111";
    i2c_sda_oen_o : out std_logic_vector(2 downto 0);
    i2c_sda_o     : out std_logic_vector(2 downto 0);
-    i2c_sda_i     : in  std_logic_vector(2 downto 0) := "111"
+    i2c_sda_i     : in  std_logic_vector(2 downto 0) := "111";
+
+    ---------------------------------------------------------------------------
+    -- Mini-backplane PWM fans
+    ---------------------------------------------------------------------------
+
+    mb_fan1_pwm_o : out std_logic;
+    mb_fan2_pwm_o : out std_logic
    );
 end scb_top_bare;

 architecture rtl of scb_top_bare is

-  constant c_NUM_WB_SLAVES : integer := 15;
+  constant c_NUM_WB_SLAVES : integer := 16;
  constant c_NUM_PORTS     : integer := g_num_ports;
  constant c_MAX_PORTS     : integer := 18;
  constant c_NUM_GL_PAUSE  : integer := 2; -- number of output global PAUSE sources for SWcore
@@ -154,19 +161,21 @@ architecture rtl of scb_top_bare is
  constant c_SLAVE_MBL_I2C0     : integer := 7;
  constant c_SLAVE_MBL_I2C1     : integer := 8;
  constant c_SLAVE_SENSOR_I2C   : integer := 9;
-  constant c_SLAVE_TRU          : integer := 10;
-  constant c_SLAVE_TATSU        : integer := 11;
-  constant c_SLAVE_PSTATS       : integer := 12;
-  constant c_SLAVE_HWDU         : integer := 13;
-  constant c_SLAVE_DUMMY        : integer := 14;
+  constant c_SLAVE_PWM          : integer := 10;
+  constant c_SLAVE_TRU          : integer := 11;
+  constant c_SLAVE_TATSU        : integer := 12;
+  constant c_SLAVE_PSTATS       : integer := 13;
+  constant c_SLAVE_HWDU         : integer := 14;
+  constant c_SLAVE_DUMMY        : integer := 15;

  constant c_cnx_base_addr : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
    (
-      x"00071000",                      -- Dummy counters
-      x"00070000",                      -- HWDU
-      x"00059000",                      -- PStats counters
-      x"00058000",                      -- TATSU
-      x"00057000",                      -- TRU
+      x"00072000",                      -- Dummy counters
+      x"00071000",                      -- HWDU
+      x"00070000",                      -- PStats counters
+      x"00059000",                      -- TATSU
+      x"00058000",                      -- TRU
+      x"00057000",                      -- PWM Controller
      x"00056000",                      -- Sensors-I2C
      x"00055000",                      -- MBL-I2C1
      x"00054000",                      -- MBL-I2C0
@@ -181,6 +190,7 @@ architecture rtl of scb_top_bare is

  constant c_cnx_base_mask : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
    (x"000ff000",
+     x"000ff000",
     x"000ff000",
     x"000ff000",
     x"000ff000",
@@ -647,14 +657,13 @@ begin
      --txtsu_timestamps(i).valid <= '0';
    end generate gen_terminate_unused_eps;

-
-    --gen_txtsu_debug: for i in 0 to c_NUM_PORTS-1 generate
-    --  TRIG0(i) <= txtsu_timestamps(i).stb;
-    --  trig1(i) <= txtsu_timestamps_ack(i);
-    --  trig2(0) <= vic_irqs(0);
-    --  trig2(1) <= vic_irqs(1);
-    --  trig2(2) <= vic_irqs(2);
-    --end generate gen_txtsu_debug;
+    gen_txtsu_debug : for i in 0 to c_NUM_PORTS-1 generate
+      TRIG0(i) <= txtsu_timestamps(i).stb;
+      trig1(i) <= txtsu_timestamps_ack(i);
+      trig2(0) <= vic_irqs(0);
+      trig2(1) <= vic_irqs(1);
+      trig2(2) <= vic_irqs(2);
+    end generate gen_txtsu_debug;

    U_Swcore : xswc_core
      generic map (
@@ -672,7 +681,7 @@ begin
        g_wb_ob_ignore_ack                => false,
        g_mpm_mem_size                    => 67584,
        g_mpm_page_size                   => 66,
-        g_mpm_ratio                       => 6, --f_swc_ratio,  --2
+        g_mpm_ratio                       => 6,  --f_swc_ratio,  --2
        g_mpm_fifo_size                   => 8,
        g_mpm_fetch_next_pg_in_advance    => false,
        g_drop_outqueue_head_on_full      => true,
@@ -859,7 +868,7 @@ begin

  uart_sel_o <= gpio_out(31);

-  
+
  gpio_o <= gpio_out;

  U_MiniBackplane_I2C0 : xwb_i2c_master
@@ -987,6 +996,23 @@ begin
    cnx_master_in(c_SLAVE_DUMMY).ack <= '1';
  end generate gen_no_dummy_rmon;

+  -----------------------------------------------------------------------------
+  -- PWM Controlle for mini-backplane fan drive
+  -----------------------------------------------------------------------------
+  
+  U_PWM_Controller : xwb_simple_pwm
+    generic map (
+      g_num_channels        => 2,
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE)
+    port map (
+      clk_sys_i => clk_sys,
+      rst_n_i   => rst_n_periph,
+      slave_i   => cnx_master_out(c_SLAVE_PWM),
+      slave_o   => cnx_master_in(c_SLAVE_PWM),
+      pwm_o(0)  => mb_fan1_pwm_o,
+      pwm_o(1)  => mb_fan2_pwm_o);
+
  -----------------------------------------------------------------------------
  -- Interrupt assignment
  -----------------------------------------------------------------------------
@@ -1001,9 +1027,9 @@ begin
 -- Various constant-driven I/Os
 -------------------------------------------------------------------------------

-  clk_en_o  <= '0';
-  clk_sel_o <= '0';
+  clk_en_o          <= '0';
+  clk_sel_o         <= '0';
  clk_dmtd_divsel_o <= '1';             -- choose 62.5 MHz DDMTD clock
-  clk_sys_o <= clk_sys;
+  clk_sys_o         <= clk_sys;
  
 end rtl;
--- a/top/scb_18ports/scb_top_synthesis.ucf
+++ b/top/scb_18ports/scb_top_synthesis.ucf
@@ -277,7 +277,8 @@ NET "mbl_scl_b[1]" LOC="AC25";
 NET "mbl_sda_b[1]" LOC="AG31"; 

 NET "clk_dmtd_divsel_o" LOC="AN15";
-NET "uart_sel_o" LOC="C12";
+NET "mb_fan1_pwm_o" LOC="C12";
+NET "mb_fan2_pwm_o" LOC="D12";


 #Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20

--- a/top/scb_18ports/scb_top_synthesis.vhd
+++ b/top/scb_18ports/scb_top_synthesis.vhd
@@ -104,7 +104,7 @@ entity scb_top_synthesis is
    clk_dmtd_divsel_o : out std_logic;

    -- UART source selection (FPGA/DBGU)
-    uart_sel_o : out std_logic;
+    -- uart_sel_o : out std_logic;

    ---------------------------------------------------------------------------
    -- GTX ports
@@ -141,7 +141,10 @@ entity scb_top_synthesis is
    mbl_sda_b : inout std_logic_vector(1 downto 0);

    sensors_scl_b: inout std_logic;
-    sensors_sda_b: inout std_logic
+    sensors_sda_b: inout std_logic;
+
+    mb_fan1_pwm_o : out std_logic;
+    mb_fan2_pwm_o : out std_logic
  );

 end scb_top_synthesis;
@@ -259,7 +262,7 @@ architecture Behavioral of scb_top_synthesis is
      uart_rxd_i          : in  std_logic;
      clk_en_o            : out std_logic;
      clk_sel_o           : out std_logic;
-      uart_sel_o          : out std_logic;
+--    uart_sel_o          : out std_logic;
      clk_dmtd_divsel_o   : out std_logic;
      phys_o              : out t_phyif_output_array(g_num_ports-1 downto 0);
      phys_i              : in  t_phyif_input_array(g_num_ports-1 downto 0);
@@ -272,7 +275,10 @@ architecture Behavioral of scb_top_synthesis is
      i2c_scl_i       : in  std_logic_vector(2 downto 0) := "111";
      i2c_sda_oen_o   : out std_logic_vector(2 downto 0);
      i2c_sda_o       : out std_logic_vector(2 downto 0);
-      i2c_sda_i       : in  std_logic_vector(2 downto 0) := "111");
+      i2c_sda_i       : in  std_logic_vector(2 downto 0) := "111";
+      mb_fan1_pwm_o   : out std_logic;
+      mb_fan2_pwm_o   : out std_logic
+      );
  end component;

  component chipscope_icon
@@ -582,7 +588,7 @@ begin
      uart_rxd_i          => uart_rxd_i,
      clk_en_o            => clk_en_o,
      clk_sel_o           => clk_sel_o,
-      uart_sel_o          => uart_sel_o,
+--    uart_sel_o          => uart_sel_o,
      clk_dmtd_divsel_o   => clk_dmtd_divsel_o,
      gpio_i              => x"00000000",
      phys_o              => to_phys(c_NUM_PORTS-1 downto 0),
@@ -594,7 +600,9 @@ begin
      i2c_scl_i       => i2c_scl_in,
      i2c_sda_oen_o   => i2c_sda_oen,
      i2c_sda_o       => i2c_sda_out,
-      i2c_sda_i       => i2c_sda_in);
+      i2c_sda_i       => i2c_sda_in,
+      mb_fan1_pwm_o   => mb_fan1_pwm_o,
+      mb_fan2_pwm_o   => mb_fan2_pwm_o);

  i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
  i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);

--- a/top/scb_8ports/scb_top_synthesis.ucf
+++ b/top/scb_8ports/scb_top_synthesis.ucf
@@ -260,7 +260,6 @@ NET "led_act_o[6]" LOC="AB27";
 NET "led_act_o[7]" LOC="AC27";  

 NET "clk_dmtd_divsel_o" LOC="AN15";
-NET "uart_sel_o" LOC="C12";


 NET "mbl_scl_b[0]" LOC="AF31"; 
@@ -268,6 +267,9 @@ NET "mbl_sda_b[0]" LOC="AG32";
 NET "mbl_scl_b[1]" LOC="AC25"; 
 NET "mbl_sda_b[1]" LOC="AG31"; 

+NET "mb_fan1_pwm_o" LOC="C12";
+NET "mb_fan2_pwm_o" LOC="D12";
+
 #Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20
 #Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/22
 NET "fpga_clk_25mhz_n_i" TNM_NET = fpga_clk_25mhz_n_i;

--- a/top/scb_8ports/scb_top_synthesis.vhd
+++ b/top/scb_8ports/scb_top_synthesis.vhd
@@ -103,7 +103,7 @@ entity scb_top_synthesis is
    clk_dmtd_divsel_o : out std_logic;

    -- UART source selection (FPGA/DBGU)
-    uart_sel_o : out std_logic;
+    -- uart_sel_o : out std_logic;

    ---------------------------------------------------------------------------
    -- GTX ports
@@ -146,7 +146,10 @@ entity scb_top_synthesis is
    mbl_sda_b : inout std_logic_vector(1 downto 0);

    sensors_scl_b: inout std_logic;
-    sensors_sda_b: inout std_logic
+    sensors_sda_b: inout std_logic;
+
+    mb_fan1_pwm_o : out std_logic;
+    mb_fan2_pwm_o : out std_logic
  );

 end scb_top_synthesis;
@@ -274,7 +277,10 @@ architecture Behavioral of scb_top_synthesis is
      i2c_scl_i       : in  std_logic_vector(2 downto 0) := "111";
      i2c_sda_oen_o   : out std_logic_vector(2 downto 0);
      i2c_sda_o       : out std_logic_vector(2 downto 0);
-      i2c_sda_i       : in  std_logic_vector(2 downto 0) := "111");
+      i2c_sda_i       : in  std_logic_vector(2 downto 0) := "111";
+      mb_fan1_pwm_o : out std_logic;
+      mb_fan2_pwm_o : out std_logic
+      );
  end component;

  component chipscope_icon
@@ -585,7 +591,7 @@ begin
      uart_rxd_i          => uart_rxd_i,
      clk_en_o            => clk_en_o,
      clk_sel_o           => clk_sel_o,
-      uart_sel_o          => uart_sel_o,
+--      uart_sel_o          => uart_sel_o,
      clk_dmtd_divsel_o   => clk_dmtd_divsel_o,
      gpio_i              => x"00000000",
      phys_o              => to_phys(c_NUM_PORTS-1 downto 0),
@@ -597,7 +603,9 @@ begin
      i2c_scl_i       => i2c_scl_in,
      i2c_sda_oen_o   => i2c_sda_oen,
      i2c_sda_o       => i2c_sda_out,
-      i2c_sda_i       => i2c_sda_in);
+      i2c_sda_i       => i2c_sda_in,
+      mb_fan1_pwm_o => mb_fan1_pwm_o,
+      mb_fan2_pwm_o => mb_fan2_pwm_o);

  i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
  i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);