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White Rabbit Switch - Gateware
Commit d6cf3c7c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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adding rmon events in NIC for per-port tx frames

parent f55d24f3
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Showing with 49 additions and 16 deletions
modules/wrsw_nic/nic_tx_fsm.vhd
View file @ d6cf3c7c
......@@ -51,7 +51,8 @@ use work.nic_wbgen2_pkg.all;
entity nic_tx_fsm is
generic(
g_port_mask_bits : integer := 32;
g_cyc_on_stall : boolean := false);
g_cyc_on_stall : boolean := false;
g_rmon_events_pp : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -117,7 +118,12 @@ entity nic_tx_fsm is
buf_grant_i : in std_logic;
-- buffer address, data and write enable lines.
buf_addr_o : out std_logic_vector(c_nic_buf_size_log2-3 downto 0);
buf_data_i : in std_logic_vector(31 downto 0)
buf_data_i : in std_logic_vector(31 downto 0);
-------------------------------------------------------------------------------
-- RMON events
-------------------------------------------------------------------------------
rmon_events_o : out std_logic_vector(g_port_mask_bits*g_rmon_events_pp-1 downto 0)
);
end nic_tx_fsm;
......@@ -155,6 +161,7 @@ architecture behavioral of nic_tx_fsm is
signal rtu_valid_int : std_logic;
signal rtu_valid_int_d0 : std_logic;
signal rtu_port_mask : std_logic_vector(g_port_mask_bits-1 downto 0);
signal tx_err : std_logic;
signal default_status_reg : t_wrf_status_reg;
......@@ -182,7 +189,8 @@ begin -- behavioral
txdesc_new_o <= cur_tx_desc;
src_o.stb <= src_stb_int;
--because it's validated with rtu_rsp_valid_o and sw_core stores it to internal register on rtu_rsp_valid strobe
rtu_dst_port_mask_o <= cur_tx_desc.dpm(g_port_mask_bits-1 downto 0);
rtu_port_mask <= cur_tx_desc.dpm(g_port_mask_bits-1 downto 0);
rtu_dst_port_mask_o <= rtu_port_mask;
rtu_prio_o <= (others => '0');
rtu_drop_o <= '0';
......@@ -513,4 +521,10 @@ begin -- behavioral
end if;
end if;
end process;
GEN_RMON: for I in 0 to g_port_mask_bits-1 generate
-- don't need to check if decision is drop, because in NIC, drop is always wired to 0
rmon_events_o(I*g_rmon_events_pp) <= rtu_valid_int and rtu_port_mask(I) and rtu_rsp_ack_i;
end generate;
end behavioral;
modules/wrsw_nic/xwrsw_nic.vhd
View file @ d6cf3c7c
......@@ -62,7 +62,8 @@ entity xwrsw_nic is
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_src_cyc_on_stall : boolean := false;
g_port_mask_bits : integer := 32); --should be num_ports+1
g_port_mask_bits : integer := 32; --should be num_ports+1
g_rmon_events_pp : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -92,7 +93,12 @@ entity xwrsw_nic is
-------------------------------------------------------------------------------
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out
wb_o : out t_wishbone_slave_out;
-------------------------------------------------------------------------------
-- RMON events
-------------------------------------------------------------------------------
rmon_events_o : out std_logic_vector(g_port_mask_bits*g_rmon_events_pp-1 downto 0)
);
end xwrsw_nic;
......@@ -209,7 +215,8 @@ architecture rtl of xwrsw_nic is
component nic_tx_fsm
generic(
g_port_mask_bits : integer := 32;
g_cyc_on_stall : boolean := false);
g_cyc_on_stall : boolean := false;
g_rmon_events_pp : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -238,7 +245,8 @@ architecture rtl of xwrsw_nic is
bna_i : in std_logic;
buf_grant_i : in std_logic;
buf_addr_o : out std_logic_vector(c_nic_buf_size_log2-3 downto 0);
buf_data_i : in std_logic_vector(31 downto 0));
buf_data_i : in std_logic_vector(31 downto 0);
rmon_events_o : out std_logic_vector(g_port_mask_bits*g_rmon_events_pp-1 downto 0));
end component;
signal rxdesc_request_next : std_logic;
......@@ -542,7 +550,8 @@ begin -- rtl
U_TX_FSM : nic_tx_fsm
generic map(
g_cyc_on_stall => g_src_cyc_on_stall,
g_port_mask_bits => g_port_mask_bits)
g_port_mask_bits => g_port_mask_bits,
g_rmon_events_pp => g_rmon_events_pp)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => nic_reset_n,
......@@ -576,7 +585,8 @@ begin -- rtl
bna_i => tx_bna,
buf_grant_i => mem_grant_tx,
buf_addr_o => mem_addr_tx,
buf_data_i => nic_mem_rd_data);
buf_data_i => nic_mem_rd_data,
rmon_events_o => rmon_events_o);
end rtl;
top/bare_top/scb_top_bare.vhd
View file @ d6cf3c7c
......@@ -196,7 +196,8 @@ architecture rtl of scb_top_bare is
constant c_DBG_V_SWCORE : integer := (3*10) + 2; -- 3 resources, each has with of CNT of 10 bits +2 to make it 32
constant c_DBG_N_REGS : integer := 1 + integer(ceil(real(c_DBG_V_SWCORE)/real(32))); -- 32-bits debug registers which go to HWIU
constant c_TRU_EVENTS : integer := 1;
constant c_ALL_EVENTS : integer := c_TRU_EVENTS + c_RTU_EVENTS + c_epevents_sz;
constant c_NIC_EVENTS : integer := 1;
constant c_ALL_EVENTS : integer := c_NIC_EVENTS + c_TRU_EVENTS + c_RTU_EVENTS + c_epevents_sz;
constant c_DUMMY_RMON : boolean := false; -- define TRUE to enable dummy_rmon module for debugging PSTAT
constant c_NUM_GPIO_PINS : integer := 1;
constant c_NUM_IRQS : integer := 4;
......@@ -302,6 +303,7 @@ architecture rtl of scb_top_bare is
-- PSTAT: RMON counters
signal rtu_events : std_logic_vector(c_NUM_PORTS*c_RTU_EVENTS -1 downto 0); --
signal ep_events : std_logic_vector(c_NUM_PORTS*c_epevents_sz -1 downto 0); --
signal nic_events : std_logic_vector((c_NUM_PORTS+1)*c_NIC_EVENTS-1 downto 0);
signal rmon_events : std_logic_vector(c_NUM_PORTS*c_ALL_EVENTS -1 downto 0); --
--TEMP
......@@ -600,7 +602,8 @@ begin
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_port_mask_bits => c_NUM_PORTS+1)
g_port_mask_bits => c_NUM_PORTS+1,
g_rmon_events_pp => c_NIC_EVENTS)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
......@@ -614,7 +617,8 @@ begin
rtu_rsp_valid_o => rtu_rsp(c_NUM_PORTS).valid,
rtu_rsp_ack_i => rtu_rsp_ack(c_NUM_PORTS),
wb_i => cnx_master_out(c_SLAVE_NIC),
wb_o => cnx_master_in(c_SLAVE_NIC));
wb_o => cnx_master_in(c_SLAVE_NIC),
rmon_events_o => nic_events);
rtu_rsp(c_NUM_PORTS).hp <= '0';
fc_rx_pause(c_NUM_PORTS) <= c_zero_pause; -- no pause for NIC
......@@ -1052,6 +1056,7 @@ begin
gen_events_assemble : for i in 0 to c_NUM_PORTS-1 generate
rmon_events((i+1)*c_ALL_EVENTS-1 downto i*c_ALL_EVENTS) <=
nic_events(i) &
std_logic(tru_resp.respMask(i) and tru_resp.valid) &
rtu_events((i+1)*c_RTU_EVENTS-1 downto i*c_RTU_EVENTS) &
ep_events ((i+1)*c_epevents_sz-1 downto i*c_epevents_sz);
......
top/bare_top/wrsw_components_pkg.vhd
View file @ d6cf3c7c
......@@ -179,7 +179,8 @@ package wrsw_components_pkg is
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_src_cyc_on_stall : boolean := false;
g_port_mask_bits : integer := 32); --should be num_ports+1
g_port_mask_bits : integer := 32; --should be num_ports+1
g_rmon_events_pp : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -193,7 +194,8 @@ package wrsw_components_pkg is
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
wb_o : out t_wishbone_slave_out;
rmon_events_o : out std_logic_vector(g_port_mask_bits*g_rmon_events_pp-1 downto 0));
end component;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ d6cf3c7c
......@@ -179,7 +179,8 @@ package wrsw_top_pkg is
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_src_cyc_on_stall : boolean := false;
g_port_mask_bits : integer := 32); --should be num_ports+1
g_port_mask_bits : integer := 32; --should be num_ports+1
g_rmon_events_pp : integer := 1);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -193,7 +194,8 @@ package wrsw_top_pkg is
rtu_rsp_valid_o : out std_logic;
rtu_rsp_ack_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
wb_o : out t_wishbone_slave_out;
rmon_events_o : out std_logic_vector(g_port_mask_bits*g_rmon_events_pp-1 downto 0));
end component;
......
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