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White Rabbit Switch - Gateware
Commit d3327d3b authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore[new_mpm]: output_block modified to talk with the new MPM

parent f01ab93d
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Showing with 455 additions and 374 deletions
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ d3327d3b
......@@ -538,30 +538,34 @@ package swc_swcore_pkg is
g_ctrl_width : integer ;--:= c_swc_ctrl_width
g_output_block_per_prio_fifo_size : integer ;--:= c_swc_output_fifo_size
g_prio_width : integer ;--:= c_swc_prio_width;, c_swc_output_prio_num_width
g_prio_num : integer --:= c_swc_output_prio_num
g_prio_num : integer ;--:= c_swc_output_prio_num
g_partial_select_width : integer;
g_wb_data_width : integer ;
g_wb_addr_width : integer ;
g_wb_sel_width : integer
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
pta_transfer_data_valid_i : in std_logic;
pta_pageaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
pta_prio_i : in std_logic_vector(g_prio_width - 1 downto 0);
pta_pck_size_i : in std_logic_vector(g_max_pck_size_width - 1 downto 0);
pta_transfer_data_ack_o : out std_logic;
mpm_pgreq_o : out std_logic;
mpm_pgaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
mpm_pckend_i : in std_logic;
mpm_pgend_i : in std_logic;
mpm_drdy_i : in std_logic;
mpm_dreq_o : out std_logic;
mpm_data_i : in std_logic_vector(g_data_width - 1 downto 0);
mpm_ctrl_i : in std_logic_vector(g_ctrl_width - 1 downto 0);
mpm_sync_i : in std_logic;
ppfm_free_o : out std_logic;
ppfm_free_done_i : in std_logic;
ppfm_free_pgaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out
pta_transfer_data_valid_i : in std_logic;
pta_pageaddr_i : in std_logic_vector(g_page_addr_width - 1 downto 0);
pta_prio_i : in std_logic_vector(g_prio_width - 1 downto 0);
pta_pck_size_i : in std_logic_vector(g_max_pck_size_width - 1 downto 0);
pta_transfer_data_ack_o : out std_logic;
mpm_d_i : in std_logic_vector (g_data_width -1 downto 0);
mpm_dvalid_i : in std_logic;
mpm_dlast_i : in std_logic;
mpm_dsel_i : in std_logic_vector (g_partial_select_width -1 downto 0);
mpm_dreq_o : out std_logic;
mpm_abort_o : out std_logic;
mpm_pg_addr_o : out std_logic_vector (g_page_addr_width -1 downto 0);
mpm_pg_valid_o : out std_logic;
mpm_pg_req_i : in std_logic;
ppfm_free_o : out std_logic;
ppfm_free_done_i : in std_logic;
ppfm_free_pgaddr_o : out std_logic_vector(g_page_addr_width - 1 downto 0);
src_i : in t_wrf_source_in;
src_o : out t_wrf_source_out
);
end component;
......
modules/wrsw_swcore/xswc_core.vhd
View file @ d3327d3b
......@@ -210,6 +210,18 @@ architecture rtl of xswc_core is
signal mpm_ctrl : std_logic_vector(g_num_ports * g_ctrl_width - 1 downto 0);
signal mpm_rd_sync : std_logic_vector(g_num_ports - 1 downto 0);
signal mpm2ob_d : std_logic_vector (g_num_ports * c_mpm_data_width -1 downto 0);
signal mpm2ob_dvalid : std_logic_vector (g_num_ports-1 downto 0);
signal mpm2ob_dlast : std_logic_vector (g_num_ports-1 downto 0);
signal mpm2ob_dsel : std_logic_vector (g_num_ports * c_partial_select_width -1 downto 0);
signal mpm2ob_pg_req : std_logic_vector (g_num_ports-1 downto 0);
signal ob2mpm_dreq : std_logic_vector (g_num_ports-1 downto 0);
signal ob2mpm_abort : std_logic_vector (g_num_ports-1 downto 0);
signal ob2mpm_pg_addr : std_logic_vector (g_num_ports * c_page_addr_width -1 downto 0);
signal ob2mpm_pg_valid : std_logic_vector (g_num_ports-1 downto 0);
----------------------------------------------------------------------------------------------------
-- signals connecting >>Muliport Memory<< with >>Linked List<< (old)
----------------------------------------------------------------------------------------------------
......@@ -395,7 +407,12 @@ architecture rtl of xswc_core is
g_ctrl_width => g_ctrl_width,
g_output_block_per_prio_fifo_size => g_output_block_per_prio_fifo_size,
g_prio_width => c_prio_width,
g_prio_num => g_prio_num
g_prio_num => g_prio_num,
g_partial_select_width => c_partial_select_width,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_wb_sel_width => g_wb_sel_width
)
port map (
clk_i => clk_i,
......@@ -420,6 +437,16 @@ architecture rtl of xswc_core is
mpm_data_i => mpm_data((i + 1) * g_wb_data_width - 1 downto i * g_wb_data_width),
mpm_ctrl_i => mpm_ctrl((i + 1) * g_ctrl_width - 1 downto i * g_ctrl_width),
mpm_sync_i => mpm_rd_sync(i),
mpm_d_i => mpm2ob_d((i+1)*c_mpm_data_width-1 downto i*c_mpm_data_width),
mpm_dvalid_i => mpm2ob_dvalid(i),
mpm_dlast_i => mpm2ob_dlast(i),
mpm_dsel_i => mpm2ob_dsel((i+1)*c_partial_select_width -1 downto i*c_partial_select_width),
mpm_dreq_o => ob2mpm_dreq(i),
mpm_abort_o => ob2mpm_abort(i),
mpm_pg_addr_o => ob2mpm_pg_addr((i+1)*c_page_addr_width downto i*c_page_addr_width),
mpm_pg_valid_o => ob2mpm_pg_valid(i),
mpm_pg_req_i => mpm2ob_pg_req(i),
-------------------------------------------------------------------------------
-- I/F with Pck's Pages Freeing Module (PPFM)
-------------------------------------------------------------------------------
......@@ -623,20 +650,20 @@ architecture rtl of xswc_core is
wport_pg_req_o => mpm2ib_pg_req,
wport_dreq_o => mpm2ib_dreq,
rport_d_o => open,
rport_dvalid_o => open,
rport_dlast_o => open,
rport_dsel_o => open,
rport_dreq_i => (others => '0'),
rport_abort_i => (others => '0'),
rport_pg_addr_i => (others => '0'),
rport_pg_valid_i => (others => '0'),
rport_pg_req_o => open,
ll_addr_o => open, -- tmp mpm2ll_addr,
rport_d_o => mpm2ob_d,
rport_dvalid_o => mpm2ob_dvalid,
rport_dlast_o => mpm2ob_dlast,
rport_dsel_o => mpm2ob_dsel,
rport_dreq_i => ob2mpm_dreq,
rport_abort_i => ob2mpm_abort,
rport_pg_addr_i => ob2mpm_pg_addr,
rport_pg_valid_i => ob2mpm_pg_valid,
rport_pg_req_o => mpm2ob_pg_req,
ll_addr_o => mpm2ll_addr, -- tmp mpm2ll_addr,
ll_data_i => ll2mpm_data
);
mpm2ll_addr <= (others => '0');
--mpm2ll_addr <= (others => '0');
----------------------------------------------------------------------
-- Page Transfer Arbiter [ 1 module]
----------------------------------------------------------------------
......
modules/wrsw_swcore/xswc_output_block.vhd
View file @ d3327d3b
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