updated afcz top level with support for sfp & hmc7044 timing fmc boards and ps only bd

d24c850b · Harvey Leicester · 02e56a36 · d24c850b · d24c850b · 02e56a36
Commit d24c850b authored Mar 19, 2024 by Harvey Leicester
6 changed files
--- a/top/afcz_wrs_8p/Manifest.py
+++ b/top/afcz_wrs_8p/Manifest.py
-files = [ "afcz_wrs_8p_top.vhd", "pins.xdc", "timing.xdc" ];
+files = [ "afcz_wrs_8p_top.vhd", "constraints.xdc" ];

 modules = { "local" : [ "../..", "../bare_top" ] };
--- a/top/afcz_wrs_8p/afcz_wrs_8p_top.vhd
+++ b/top/afcz_wrs_8p/afcz_wrs_8p_top.vhd
--- a/top/afcz_wrs_8p/bd.tcl
+++ b/top/afcz_wrs_8p/bd.tcl
--- a/top/afcz_wrs_8p/pins.xdc
+++ b/top/afcz_wrs_8p/pins.xdc
--- a/top/afcz_wrs_8p/project.tcl
+++ b/top/afcz_wrs_8p/project.tcl
--- a/top/afcz_wrs_8p/timing.xdc
+++ b/top/afcz_wrs_8p/timing.xdc
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-#
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-create_clock -period 8.000 -name mgtclk1_224_p_i -waveform {0.000 4.000} [get_ports mgtclk1_224_p_i]
-create_clock -period 50.000 -name clk_20m_vcxo1_i -waveform {0.000 25.000} [get_ports clk_20m_vcxo1_i]
-set_false_path -from [get_clocks I] -to [get_clocks {from_phys[0][tx_out_clk]}]
-set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]}]
-set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_1}]
-set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_2}]
-set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_3}]
-set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_4}]
-set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_5}]
-set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_6}]
-set_false_path -from [get_clocks I] -to [get_clocks {rxoutclk_out[0]_7}]
-create_clock -period 16.000 -name clk_rx0 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[0].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
-create_clock -period 16.000 -name clk_rx1 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[1].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
-create_clock -period 16.000 -name clk_rx2 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[2].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
-create_clock -period 16.000 -name clk_rx3 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[3].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
-create_clock -period 16.000 -name clk_rx4 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[4].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
-create_clock -period 16.000 -name clk_rx5 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[5].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
-create_clock -period 16.000 -name clk_rx6 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[6].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
-create_clock -period 16.000 -name clk_rx7 -waveform {0.000 8.000} [get_nets {top_i/afcz_wrs_8p_top_0/inst/gen_phys[7].U_PHY/U_gtwizard_gthe4/inst/gen_gtwizard_gthe4_top.gtwizard_ultrascale_2_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[0].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/rxoutclk_out[0]}]
-create_generated_clock -name clk_dmtd_62_5 -source [get_pins top_i/afcz_wrs_8p_top_0/inst/U_DMTD_Clock_PLL/CLKIN1] -master_clock clk_20m_vcxo1_i [get_pins top_i/afcz_wrs_8p_top_0/inst/U_DMTD_Clock_PLL/CLKOUT0]
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