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White Rabbit Switch - Gateware
Commit cf32272e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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top levels: added I2C master for TMP101 onboard temperature sensors and rewired… 

top levels: added I2C master for TMP101 onboard temperature sensors and rewired pll_status_i to v3.2. dedicated clock input
parent 47932148
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Showing with 148 additions and 88 deletions
top/bare_top/scb_top_bare.vhd
View file @ cf32272e
......@@ -112,21 +112,23 @@ entity scb_top_bare is
gpio_i : in std_logic_vector(31 downto 0);
---------------------------------------------------------------------------
-- Mini-backplane I/O
-- I2C I/Os
-- mapping: 0/1 -> MiniBackplane busses 0/1
-- 2 -> Onboard temp sensors
---------------------------------------------------------------------------
i2c_mbl_scl_oen_o : out std_logic_vector(1 downto 0);
i2c_mbl_scl_o : out std_logic_vector(1 downto 0);
i2c_mbl_scl_i : in std_logic_vector(1 downto 0) := "11";
i2c_mbl_sda_oen_o : out std_logic_vector(1 downto 0);
i2c_mbl_sda_o : out std_logic_vector(1 downto 0);
i2c_mbl_sda_i : in std_logic_vector(1 downto 0) := "11"
i2c_scl_oen_o : out std_logic_vector(2 downto 0);
i2c_scl_o : out std_logic_vector(2 downto 0);
i2c_scl_i : in std_logic_vector(2 downto 0) := "111";
i2c_sda_oen_o : out std_logic_vector(2 downto 0);
i2c_sda_o : out std_logic_vector(2 downto 0);
i2c_sda_i : in std_logic_vector(2 downto 0) := "111"
);
end scb_top_bare;
architecture rtl of scb_top_bare is
constant c_NUM_WB_SLAVES : integer := 9;
constant c_NUM_WB_SLAVES : integer := 10;
constant c_NUM_PORTS : integer := g_num_ports;
constant c_MAX_PORTS : integer := 18;
......@@ -144,9 +146,11 @@ architecture rtl of scb_top_bare is
constant c_SLAVE_GPIO : integer := 6;
constant c_SLAVE_MBL_I2C0 : integer := 7;
constant c_SLAVE_MBL_I2C1 : integer := 8;
constant c_SLAVE_SENSOR_I2C : integer := 9;
constant c_cnx_base_addr : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
(
x"00056000", -- Sensors-I2C
x"00055000", -- MBL-I2C1
x"00054000", -- MBL-I2C0
x"00053000", -- GPIO
......@@ -160,6 +164,7 @@ architecture rtl of scb_top_bare is
constant c_cnx_base_mask : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
(x"000ff000",
x"000ff000",
x"000ff000",
x"000ff000",
x"000f0000",
......@@ -684,12 +689,12 @@ begin
slave_i => cnx_master_out(c_SLAVE_MBL_I2C0),
slave_o => cnx_master_in(c_SLAVE_MBL_I2C0),
desc_o => open,
scl_pad_i => i2c_mbl_scl_i(0),
scl_pad_o => i2c_mbl_scl_o(0),
scl_padoen_o => i2c_mbl_scl_oen_o(0),
sda_pad_i => i2c_mbl_sda_i(0),
sda_pad_o => i2c_mbl_sda_o(0),
sda_padoen_o => i2c_mbl_sda_oen_o(0));
scl_pad_i => i2c_scl_i(0),
scl_pad_o => i2c_scl_o(0),
scl_padoen_o => i2c_scl_oen_o(0),
sda_pad_i => i2c_sda_i(0),
sda_pad_o => i2c_sda_o(0),
sda_padoen_o => i2c_sda_oen_o(0));
U_MiniBackplane_I2C1 : xwb_i2c_master
generic map (
......@@ -701,12 +706,29 @@ begin
slave_i => cnx_master_out(c_SLAVE_MBL_I2C1),
slave_o => cnx_master_in(c_SLAVE_MBL_I2C1),
desc_o => open,
scl_pad_i => i2c_mbl_scl_i(1),
scl_pad_o => i2c_mbl_scl_o(1),
scl_padoen_o => i2c_mbl_scl_oen_o(1),
sda_pad_i => i2c_mbl_sda_i(1),
sda_pad_o => i2c_mbl_sda_o(1),
sda_padoen_o => i2c_mbl_sda_oen_o(1));
scl_pad_i => i2c_scl_i(1),
scl_pad_o => i2c_scl_o(1),
scl_padoen_o => i2c_scl_oen_o(1),
sda_pad_i => i2c_sda_i(1),
sda_pad_o => i2c_sda_o(1),
sda_padoen_o => i2c_sda_oen_o(1));
U_Sensors_I2C : xwb_i2c_master
generic map (
g_interface_mode => PIPELINED,
g_address_granularity => BYTE)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_periph,
slave_i => cnx_master_out(c_SLAVE_SENSOR_I2C),
slave_o => cnx_master_in(c_SLAVE_SENSOR_I2C),
desc_o => open,
scl_pad_i => i2c_scl_i(2),
scl_pad_o => i2c_scl_o(2),
scl_padoen_o => i2c_scl_oen_o(2),
sda_pad_i => i2c_sda_i(2),
sda_pad_o => i2c_sda_o(2),
sda_padoen_o => i2c_sda_oen_o(2));
-----------------------------------------------------------------------------
-- Interrupt assignment
......
top/bare_top/scb_top_sim.vhd
View file @ cf32272e
......@@ -108,17 +108,18 @@ architecture rtl of scb_top_sim is
signal phys_in : t_phyif_input_array(g_num_ports-1 downto 0);
signal cpu_irq_n : std_logic;
signal i2c_mbl_scl_oen : std_logic_vector(1 downto 0);
signal i2c_mbl_scl_out : std_logic_vector(1 downto 0);
signal i2c_mbl_sda_oen : std_logic_vector(1 downto 0);
signal i2c_mbl_sda_out : std_logic_vector(1 downto 0);
signal i2c_scl_oen : std_logic_vector(2 downto 0);
signal i2c_scl_out : std_logic_vector(2 downto 0);
signal i2c_scl_in : std_logic_vector(2 downto 0);
signal i2c_sda_oen : std_logic_vector(2 downto 0);
signal i2c_sda_out : std_logic_vector(2 downto 0);
signal i2c_sda_in : std_logic_vector(2 downto 0);
begin -- rtl
gen_i2c_tribufs : for i in 0 to 1 generate
mbl_scl_b(i) <= i2c_mbl_scl_out(i) when i2c_mbl_scl_oen(i) = '0' else 'Z';
mbl_sda_b(i) <= i2c_mbl_sda_out(i) when i2c_mbl_sda_oen(i) = '0' else 'Z';
mbl_scl_b(i) <= i2c_scl_out(i) when i2c_scl_oen(i) = '0' else 'Z';
mbl_sda_b(i) <= i2c_sda_out(i) when i2c_sda_oen(i) = '0' else 'Z';
end generate gen_i2c_tribufs;
cpu_wb_in.adr <= wb_adr_i;
......@@ -172,12 +173,12 @@ begin -- rtl
led_act_o => led_act_o,
gpio_o => open,
gpio_i => (others => '0'),
i2c_mbl_scl_oen_o => i2c_mbl_scl_oen,
i2c_mbl_scl_o => i2c_mbl_scl_out,
i2c_mbl_scl_i => mbl_scl_b,
i2c_mbl_sda_oen_o => i2c_mbl_sda_oen,
i2c_mbl_sda_o => i2c_mbl_sda_out,
i2c_mbl_sda_i => mbl_sda_b
i2c_scl_oen_o => i2c_scl_oen,
i2c_scl_o => i2c_scl_out,
i2c_scl_i => i2c_scl_in,
i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in
);
gen_phys : for i in 0 to g_num_ports-1 generate
......
top/bare_top/wrsw_top_pkg.vhd
View file @ cf32272e
......@@ -250,12 +250,12 @@ package wrsw_top_pkg is
led_act_o : out std_logic_vector(g_num_ports-1 downto 0);
gpio_o : out std_logic_vector(31 downto 0);
gpio_i : in std_logic_vector(31 downto 0);
i2c_mbl_scl_oen_o : out std_logic_vector(1 downto 0);
i2c_mbl_scl_o : out std_logic_vector(1 downto 0);
i2c_mbl_scl_i : in std_logic_vector(1 downto 0) := "11";
i2c_mbl_sda_oen_o : out std_logic_vector(1 downto 0);
i2c_mbl_sda_o : out std_logic_vector(1 downto 0);
i2c_mbl_sda_i : in std_logic_vector(1 downto 0) := "11");
i2c_scl_oen_o : out std_logic_vector(2 downto 0);
i2c_scl_o : out std_logic_vector(2 downto 0);
i2c_scl_i : in std_logic_vector(2 downto 0) := "111";
i2c_sda_oen_o : out std_logic_vector(2 downto 0);
i2c_sda_o : out std_logic_vector(2 downto 0);
i2c_sda_i : in std_logic_vector(2 downto 0) := "111");
end component;
component xswc_core is
generic(
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ cf32272e
......@@ -13,6 +13,10 @@ NET "fpga_clk_aux_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
#EBI BUS
#NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34";
......@@ -96,7 +100,7 @@ NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="AE18";
NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "uart_txd_o" LOC="E11";
......@@ -344,7 +348,7 @@ TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
INST "cmp_wb_cpu_bridge/gen_sync_chains_nosim.sync_ffs_wr/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/gen_network_stuff.gen_endpoints_and_phys[0].U_Endpoint_X/U_Wrapped_Endpoint/gen_leds.U_Led_Ctrl/U_Sync_Activity/sync0" TNM = Ignore_sync_ffs;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ cf32272e
......@@ -138,9 +138,11 @@ entity scb_top_synthesis is
led_act_o : out std_logic_vector(17 downto 0);
mbl_scl_b : inout std_logic_vector(1 downto 0);
mbl_sda_b : inout std_logic_vector(1 downto 0)
mbl_sda_b : inout std_logic_vector(1 downto 0);
);
sensors_scl_b: inout std_logic;
sensors_sda_b: inout std_logic
);
end scb_top_synthesis;
......@@ -214,11 +216,12 @@ architecture Behavioral of scb_top_synthesis is
signal top_master_in, bridge_master_in : t_wishbone_master_in;
signal top_master_out, bridge_master_out : t_wishbone_master_out;
signal i2c_mbl_scl_oen : std_logic_vector(1 downto 0);
signal i2c_mbl_scl_out : std_logic_vector(1 downto 0);
signal i2c_mbl_sda_oen : std_logic_vector(1 downto 0);
signal i2c_mbl_sda_out : std_logic_vector(1 downto 0);
signal i2c_scl_oen : std_logic_vector(2 downto 0);
signal i2c_scl_out : std_logic_vector(2 downto 0);
signal i2c_sda_oen : std_logic_vector(2 downto 0);
signal i2c_sda_out : std_logic_vector(2 downto 0);
signal i2c_sda_in : std_logic_vector(2 downto 0);
signal i2c_scl_in : std_logic_vector(2 downto 0);
component scb_top_bare
generic (
g_num_ports : integer;
......@@ -261,12 +264,12 @@ architecture Behavioral of scb_top_synthesis is
led_act_o : out std_logic_vector(g_num_ports-1 downto 0);
gpio_o : out std_logic_vector(31 downto 0);
gpio_i : in std_logic_vector(31 downto 0);
i2c_mbl_scl_oen_o : out std_logic_vector(1 downto 0);
i2c_mbl_scl_o : out std_logic_vector(1 downto 0);
i2c_mbl_scl_i : in std_logic_vector(1 downto 0) := "11";
i2c_mbl_sda_oen_o : out std_logic_vector(1 downto 0);
i2c_mbl_sda_o : out std_logic_vector(1 downto 0);
i2c_mbl_sda_i : in std_logic_vector(1 downto 0) := "11");
i2c_scl_oen_o : out std_logic_vector(2 downto 0);
i2c_scl_o : out std_logic_vector(2 downto 0);
i2c_scl_i : in std_logic_vector(2 downto 0) := "111";
i2c_sda_oen_o : out std_logic_vector(2 downto 0);
i2c_sda_o : out std_logic_vector(2 downto 0);
i2c_sda_i : in std_logic_vector(2 downto 0) := "111");
end component;
component chipscope_icon
......@@ -291,10 +294,6 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
gen_i2c_tribufs : for i in 0 to 1 generate
mbl_scl_b(i) <= i2c_mbl_scl_out(i) when i2c_mbl_scl_oen(i) = '0' else 'Z';
mbl_sda_b(i) <= i2c_mbl_sda_out(i) when i2c_mbl_sda_oen(i) = '0' else 'Z';
end generate gen_i2c_tribufs;
--chipscope_icon_1 : chipscope_icon
-- port map (
......@@ -584,12 +583,27 @@ begin
phys_i => from_phys(c_NUM_PORTS-1 downto 0),
-- led_link_o => led_link_o,
led_act_o => led_act_o(c_NUM_PORTS-1 downto 0),
i2c_mbl_scl_oen_o => i2c_mbl_scl_oen,
i2c_mbl_scl_o => i2c_mbl_scl_out,
i2c_mbl_scl_i => mbl_scl_b,
i2c_mbl_sda_oen_o => i2c_mbl_sda_oen,
i2c_mbl_sda_o => i2c_mbl_sda_out,
i2c_mbl_sda_i => mbl_sda_b);
i2c_scl_oen_o => i2c_scl_oen,
i2c_scl_o => i2c_scl_out,
i2c_scl_i => i2c_scl_in,
i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in);
i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);
i2c_scl_in(2) <= sensors_scl_b;
i2c_sda_in(2) <= sensors_sda_b;
gen_i2c_tribufs : for i in 0 to 1 generate
mbl_scl_b(i) <= i2c_scl_out(i) when i2c_scl_oen(i) = '0' else 'Z';
mbl_sda_b(i) <= i2c_sda_out(i) when i2c_sda_oen(i) = '0' else 'Z';
end generate gen_i2c_tribufs;
sensors_scl_b <= i2c_scl_out(2) when i2c_scl_oen(2) = '0' else 'Z';
sensors_sda_b <= i2c_sda_out(2) when i2c_sda_oen(2) = '0' else 'Z';
end Behavioral;
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ cf32272e
......@@ -13,6 +13,10 @@ NET "fpga_clk_aux_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
#EBI BUS
#NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34";
......@@ -96,7 +100,7 @@ NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="AE18";
NET "pll_status_i" LOC="K13";
NET "pll_sync_n_o" LOC="AG18";
NET "uart_txd_o" LOC="E11";
......@@ -353,4 +357,4 @@ TIMESPEC TS_gtx16_19_clk_n_i = PERIOD "gtx16_19_clk_n_i" 8 ns HIGH 50%;
NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
\ No newline at end of file
#NET "pll_status_i" CLOCK_DEDICATED_ROUTE = FALSE;
\ No newline at end of file
top/scb_8ports/scb_top_synthesis.vhd
View file @ cf32272e
......@@ -143,9 +143,11 @@ entity scb_top_synthesis is
led_act_o : out std_logic_vector(7 downto 0);
mbl_scl_b : inout std_logic_vector(1 downto 0);
mbl_sda_b : inout std_logic_vector(1 downto 0)
mbl_sda_b : inout std_logic_vector(1 downto 0);
);
sensors_scl_b: inout std_logic;
sensors_sda_b: inout std_logic
);
end scb_top_synthesis;
......@@ -215,10 +217,12 @@ architecture Behavioral of scb_top_synthesis is
signal top_master_in, bridge_master_in : t_wishbone_master_in;
signal top_master_out, bridge_master_out : t_wishbone_master_out;
signal i2c_mbl_scl_oen : std_logic_vector(1 downto 0);
signal i2c_mbl_scl_out : std_logic_vector(1 downto 0);
signal i2c_mbl_sda_oen : std_logic_vector(1 downto 0);
signal i2c_mbl_sda_out : std_logic_vector(1 downto 0);
signal i2c_scl_oen : std_logic_vector(2 downto 0);
signal i2c_scl_out : std_logic_vector(2 downto 0);
signal i2c_sda_oen : std_logic_vector(2 downto 0);
signal i2c_sda_out : std_logic_vector(2 downto 0);
signal i2c_sda_in : std_logic_vector(2 downto 0);
signal i2c_scl_in : std_logic_vector(2 downto 0);
component scb_top_bare
generic (
......@@ -262,12 +266,12 @@ architecture Behavioral of scb_top_synthesis is
led_act_o : out std_logic_vector(g_num_ports-1 downto 0);
gpio_o : out std_logic_vector(31 downto 0);
gpio_i : in std_logic_vector(31 downto 0);
i2c_mbl_scl_oen_o : out std_logic_vector(1 downto 0);
i2c_mbl_scl_o : out std_logic_vector(1 downto 0);
i2c_mbl_scl_i : in std_logic_vector(1 downto 0) := "11";
i2c_mbl_sda_oen_o : out std_logic_vector(1 downto 0);
i2c_mbl_sda_o : out std_logic_vector(1 downto 0);
i2c_mbl_sda_i : in std_logic_vector(1 downto 0) := "11");
i2c_scl_oen_o : out std_logic_vector(2 downto 0);
i2c_scl_o : out std_logic_vector(2 downto 0);
i2c_scl_i : in std_logic_vector(2 downto 0) := "111";
i2c_sda_oen_o : out std_logic_vector(2 downto 0);
i2c_sda_o : out std_logic_vector(2 downto 0);
i2c_sda_i : in std_logic_vector(2 downto 0) := "111");
end component;
component chipscope_icon
......@@ -292,10 +296,6 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
gen_i2c_tribufs : for i in 0 to 1 generate
mbl_scl_b(i) <= i2c_mbl_scl_out(i) when i2c_mbl_scl_oen(i) = '0' else 'Z';
mbl_sda_b(i) <= i2c_mbl_sda_out(i) when i2c_mbl_sda_oen(i) = '0' else 'Z';
end generate gen_i2c_tribufs;
--chipscope_icon_1 : chipscope_icon
-- port map (
......@@ -586,12 +586,27 @@ begin
phys_i => from_phys(c_NUM_PORTS-1 downto 0),
-- led_link_o => led_link_o,
led_act_o => led_act_o(c_NUM_PORTS-1 downto 0),
i2c_mbl_scl_oen_o => i2c_mbl_scl_oen,
i2c_mbl_scl_o => i2c_mbl_scl_out,
i2c_mbl_scl_i => mbl_scl_b,
i2c_mbl_sda_oen_o => i2c_mbl_sda_oen,
i2c_mbl_sda_o => i2c_mbl_sda_out,
i2c_mbl_sda_i => mbl_sda_b);
i2c_scl_oen_o => i2c_scl_oen,
i2c_scl_o => i2c_scl_out,
i2c_scl_i => i2c_scl_in,
i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in);
i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);
i2c_scl_in(2) <= sensors_scl_b;
i2c_sda_in(2) <= sensors_sda_b;
gen_i2c_tribufs : for i in 0 to 1 generate
mbl_scl_b(i) <= i2c_scl_out(i) when i2c_scl_oen(i) = '0' else 'Z';
mbl_sda_b(i) <= i2c_sda_out(i) when i2c_sda_oen(i) = '0' else 'Z';
end generate gen_i2c_tribufs;
sensors_scl_b <= i2c_scl_out(2) when i2c_scl_oen(2) = '0' else 'Z';
sensors_sda_b <= i2c_sda_out(2) when i2c_sda_oen(2) = '0' else 'Z';
end Behavioral;
......
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