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White Rabbit Switch - Gateware
Commits
c7e859e9
Commit
c7e859e9
authored
Aug 01, 2016
by
Grzegorz Daniluk
Browse files
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wrsw_nic: Random Early Detection for b/w throttling
parent
55291edc
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5 changed files
with
195 additions
and
106 deletions
+195
-106
nic_bw_throttling.vhd
modules/wrsw_nic/nic_bw_throttling.vhd
+131
-82
nic_rx_fsm.vhd
modules/wrsw_nic/nic_rx_fsm.vhd
+19
-4
nic_wbgen2_pkg.vhd
modules/wrsw_nic/nic_wbgen2_pkg.vhd
+12
-8
nic_wishbone_slave.vhd
modules/wrsw_nic/nic_wishbone_slave.vhd
+25
-4
wr_nic.wb
modules/wrsw_nic/wr_nic.wb
+8
-8
No files found.
modules/wrsw_nic/nic_bw_throttling.vhd
View file @
c7e859e9
This diff is collapsed.
Click to expand it.
modules/wrsw_nic/nic_rx_fsm.vhd
View file @
c7e859e9
...
@@ -133,8 +133,9 @@ architecture behavioral of NIC_RX_FSM is
...
@@ -133,8 +133,9 @@ architecture behavioral of NIC_RX_FSM is
snk_o
:
out
t_wrf_sink_out
;
snk_o
:
out
t_wrf_sink_out
;
src_o
:
out
t_wrf_source_out
;
src_o
:
out
t_wrf_source_out
;
src_i
:
in
t_wrf_source_in
;
src_i
:
in
t_wrf_source_in
;
bw_o
:
out
std_logic_vector
(
31
downto
0
);
new_limit_i
:
in
std_logic
;
rnd_o
:
out
std_logic_vector
(
31
downto
0
));
bwmax_kbps_i
:
in
unsigned
(
15
downto
0
);
bw_bps_o
:
out
std_logic_vector
(
31
downto
0
));
end
component
;
end
component
;
...
@@ -166,6 +167,7 @@ architecture behavioral of NIC_RX_FSM is
...
@@ -166,6 +167,7 @@ architecture behavioral of NIC_RX_FSM is
signal
bw_src_out
:
t_wrf_source_out
;
signal
bw_src_out
:
t_wrf_source_out
;
signal
bw_src_in
:
t_wrf_source_in
;
signal
bw_src_in
:
t_wrf_source_in
;
signal
max_bw_reg
:
std_logic_vector
(
15
downto
0
);
begin
begin
...
@@ -179,8 +181,21 @@ begin
...
@@ -179,8 +181,21 @@ begin
snk_o
=>
snk_o
,
snk_o
=>
snk_o
,
src_o
=>
bw_src_out
,
src_o
=>
bw_src_out
,
src_i
=>
bw_src_in
,
src_i
=>
bw_src_in
,
bw_o
=>
regs_o
.
bw_i
,
new_limit_i
=>
regs_i
.
maxrxbw_load_o
,
rnd_o
=>
regs_o
.
rnd_i
);
bwmax_kbps_i
=>
unsigned
(
regs_i
.
maxrxbw_o
),
bw_bps_o
=>
regs_o
.
rxbw_i
);
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_n_i
=
'0'
then
max_bw_reg
<=
(
others
=>
'0'
);
elsif
regs_i
.
maxrxbw_load_o
=
'1'
then
max_bw_reg
<=
regs_i
.
maxrxbw_o
;
end
if
;
end
if
;
end
process
;
regs_o
.
maxrxbw_i
<=
max_bw_reg
;
U_Buffer
:
nic_elastic_buffer
U_Buffer
:
nic_elastic_buffer
generic
map
(
generic
map
(
...
...
modules/wrsw_nic/nic_wbgen2_pkg.vhd
View file @
c7e859e9
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : nic_wbgen2_pkg.vhd
-- File : nic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created :
Thu Jul 28 10:18:55
2016
-- Created :
Mon Aug 1 16:03:57
2016
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
...
@@ -27,8 +27,8 @@ package nic_wbgen2_pkg is
...
@@ -27,8 +27,8 @@ package nic_wbgen2_pkg is
sr_tx_error_i
:
std_logic
;
sr_tx_error_i
:
std_logic
;
sr_cur_tx_desc_i
:
std_logic_vector
(
2
downto
0
);
sr_cur_tx_desc_i
:
std_logic_vector
(
2
downto
0
);
sr_cur_rx_desc_i
:
std_logic_vector
(
2
downto
0
);
sr_cur_rx_desc_i
:
std_logic_vector
(
2
downto
0
);
bw_i
:
std_logic_vector
(
31
downto
0
);
rxbw_i
:
std_logic_vector
(
31
downto
0
);
rnd_i
:
std_logic_vector
(
31
downto
0
);
maxrxbw_i
:
std_logic_vector
(
15
downto
0
);
end
record
;
end
record
;
constant
c_nic_in_registers_init_value
:
t_nic_in_registers
:
=
(
constant
c_nic_in_registers_init_value
:
t_nic_in_registers
:
=
(
...
@@ -38,8 +38,8 @@ package nic_wbgen2_pkg is
...
@@ -38,8 +38,8 @@ package nic_wbgen2_pkg is
sr_tx_error_i
=>
'0'
,
sr_tx_error_i
=>
'0'
,
sr_cur_tx_desc_i
=>
(
others
=>
'0'
),
sr_cur_tx_desc_i
=>
(
others
=>
'0'
),
sr_cur_rx_desc_i
=>
(
others
=>
'0'
),
sr_cur_rx_desc_i
=>
(
others
=>
'0'
),
bw_i
=>
(
others
=>
'0'
),
rx
bw_i
=>
(
others
=>
'0'
),
rnd
_i
=>
(
others
=>
'0'
)
maxrxbw
_i
=>
(
others
=>
'0'
)
);
);
-- Output registers (WB slave -> user design)
-- Output registers (WB slave -> user design)
...
@@ -54,6 +54,8 @@ package nic_wbgen2_pkg is
...
@@ -54,6 +54,8 @@ package nic_wbgen2_pkg is
sr_tx_done_load_o
:
std_logic
;
sr_tx_done_load_o
:
std_logic
;
sr_tx_error_o
:
std_logic
;
sr_tx_error_o
:
std_logic
;
sr_tx_error_load_o
:
std_logic
;
sr_tx_error_load_o
:
std_logic
;
maxrxbw_o
:
std_logic_vector
(
15
downto
0
);
maxrxbw_load_o
:
std_logic
;
end
record
;
end
record
;
constant
c_nic_out_registers_init_value
:
t_nic_out_registers
:
=
(
constant
c_nic_out_registers_init_value
:
t_nic_out_registers
:
=
(
...
@@ -65,7 +67,9 @@ package nic_wbgen2_pkg is
...
@@ -65,7 +67,9 @@ package nic_wbgen2_pkg is
sr_tx_done_o
=>
'0'
,
sr_tx_done_o
=>
'0'
,
sr_tx_done_load_o
=>
'0'
,
sr_tx_done_load_o
=>
'0'
,
sr_tx_error_o
=>
'0'
,
sr_tx_error_o
=>
'0'
,
sr_tx_error_load_o
=>
'0'
sr_tx_error_load_o
=>
'0'
,
maxrxbw_o
=>
(
others
=>
'0'
),
maxrxbw_load_o
=>
'0'
);
);
function
"or"
(
left
,
right
:
t_nic_in_registers
)
return
t_nic_in_registers
;
function
"or"
(
left
,
right
:
t_nic_in_registers
)
return
t_nic_in_registers
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
function
f_x_to_zero
(
x
:
std_logic
)
return
std_logic
;
...
@@ -102,8 +106,8 @@ tmp.sr_tx_done_i := f_x_to_zero(left.sr_tx_done_i) or f_x_to_zero(right.sr_tx_do
...
@@ -102,8 +106,8 @@ tmp.sr_tx_done_i := f_x_to_zero(left.sr_tx_done_i) or f_x_to_zero(right.sr_tx_do
tmp
.
sr_tx_error_i
:
=
f_x_to_zero
(
left
.
sr_tx_error_i
)
or
f_x_to_zero
(
right
.
sr_tx_error_i
);
tmp
.
sr_tx_error_i
:
=
f_x_to_zero
(
left
.
sr_tx_error_i
)
or
f_x_to_zero
(
right
.
sr_tx_error_i
);
tmp
.
sr_cur_tx_desc_i
:
=
f_x_to_zero
(
left
.
sr_cur_tx_desc_i
)
or
f_x_to_zero
(
right
.
sr_cur_tx_desc_i
);
tmp
.
sr_cur_tx_desc_i
:
=
f_x_to_zero
(
left
.
sr_cur_tx_desc_i
)
or
f_x_to_zero
(
right
.
sr_cur_tx_desc_i
);
tmp
.
sr_cur_rx_desc_i
:
=
f_x_to_zero
(
left
.
sr_cur_rx_desc_i
)
or
f_x_to_zero
(
right
.
sr_cur_rx_desc_i
);
tmp
.
sr_cur_rx_desc_i
:
=
f_x_to_zero
(
left
.
sr_cur_rx_desc_i
)
or
f_x_to_zero
(
right
.
sr_cur_rx_desc_i
);
tmp
.
bw_i
:
=
f_x_to_zero
(
left
.
bw_i
)
or
f_x_to_zero
(
right
.
bw_i
);
tmp
.
rxbw_i
:
=
f_x_to_zero
(
left
.
rxbw_i
)
or
f_x_to_zero
(
right
.
rx
bw_i
);
tmp
.
rnd_i
:
=
f_x_to_zero
(
left
.
rnd_i
)
or
f_x_to_zero
(
right
.
rnd
_i
);
tmp
.
maxrxbw_i
:
=
f_x_to_zero
(
left
.
maxrxbw_i
)
or
f_x_to_zero
(
right
.
maxrxbw
_i
);
return
tmp
;
return
tmp
;
end
function
;
end
function
;
end
package
body
;
end
package
body
;
modules/wrsw_nic/nic_wishbone_slave.vhd
View file @
c7e859e9
...
@@ -3,7 +3,7 @@
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- File : nic_wishbone_slave.vhd
-- File : nic_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Author : auto-generated by wbgen2 from wr_nic.wb
-- Created :
Thu Jul 28 10:18:55
2016
-- Created :
Mon Aug 1 16:03:57
2016
-- Standard : VHDL'87
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
...
@@ -120,6 +120,7 @@ begin
...
@@ -120,6 +120,7 @@ begin
regs_o
.
sr_rec_load_o
<=
'0'
;
regs_o
.
sr_rec_load_o
<=
'0'
;
regs_o
.
sr_tx_done_load_o
<=
'0'
;
regs_o
.
sr_tx_done_load_o
<=
'0'
;
regs_o
.
sr_tx_error_load_o
<=
'0'
;
regs_o
.
sr_tx_error_load_o
<=
'0'
;
regs_o
.
maxrxbw_load_o
<=
'0'
;
eic_idr_write_int
<=
'0'
;
eic_idr_write_int
<=
'0'
;
eic_ier_write_int
<=
'0'
;
eic_ier_write_int
<=
'0'
;
eic_isr_write_int
<=
'0'
;
eic_isr_write_int
<=
'0'
;
...
@@ -133,6 +134,7 @@ begin
...
@@ -133,6 +134,7 @@ begin
regs_o
.
sr_rec_load_o
<=
'0'
;
regs_o
.
sr_rec_load_o
<=
'0'
;
regs_o
.
sr_tx_done_load_o
<=
'0'
;
regs_o
.
sr_tx_done_load_o
<=
'0'
;
regs_o
.
sr_tx_error_load_o
<=
'0'
;
regs_o
.
sr_tx_error_load_o
<=
'0'
;
regs_o
.
maxrxbw_load_o
<=
'0'
;
eic_idr_write_int
<=
'0'
;
eic_idr_write_int
<=
'0'
;
eic_ier_write_int
<=
'0'
;
eic_ier_write_int
<=
'0'
;
eic_isr_write_int
<=
'0'
;
eic_isr_write_int
<=
'0'
;
...
@@ -141,6 +143,7 @@ begin
...
@@ -141,6 +143,7 @@ begin
regs_o
.
sr_rec_load_o
<=
'0'
;
regs_o
.
sr_rec_load_o
<=
'0'
;
regs_o
.
sr_tx_done_load_o
<=
'0'
;
regs_o
.
sr_tx_done_load_o
<=
'0'
;
regs_o
.
sr_tx_error_load_o
<=
'0'
;
regs_o
.
sr_tx_error_load_o
<=
'0'
;
regs_o
.
maxrxbw_load_o
<=
'0'
;
end
if
;
end
if
;
else
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
...
@@ -226,13 +229,30 @@ begin
...
@@ -226,13 +229,30 @@ begin
when
"0010"
=>
when
"0010"
=>
if
(
wb_we_i
=
'1'
)
then
if
(
wb_we_i
=
'1'
)
then
end
if
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
bw_i
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rx
bw_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"0011"
=>
when
"0011"
=>
if
(
wb_we_i
=
'1'
)
then
if
(
wb_we_i
=
'1'
)
then
regs_o
.
maxrxbw_load_o
<=
'1'
;
end
if
;
end
if
;
rddata_reg
(
31
downto
0
)
<=
regs_i
.
rnd_i
;
rddata_reg
(
15
downto
0
)
<=
regs_i
.
maxrxbw_i
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1000"
=>
when
"1000"
=>
...
@@ -473,7 +493,8 @@ begin
...
@@ -473,7 +493,8 @@ begin
-- Current TX descriptor
-- Current TX descriptor
-- Current RX descriptor
-- Current RX descriptor
-- Bytes-per-second
-- Bytes-per-second
-- 32-bit random number for throttling
-- KBytes-per-second
regs_o
.
maxrxbw_o
<=
wrdata_reg
(
15
downto
0
);
-- extra code for reg/fifo/mem: TX descriptors mem
-- extra code for reg/fifo/mem: TX descriptors mem
-- RAM block instantiation for memory: TX descriptors mem
-- RAM block instantiation for memory: TX descriptors mem
nic_dtx_raminst
:
wbgen2_dpssram
nic_dtx_raminst
:
wbgen2_dpssram
...
...
modules/wrsw_nic/wr_nic.wb
View file @
c7e859e9
...
@@ -153,8 +153,8 @@ top = peripheral {
...
@@ -153,8 +153,8 @@ top = peripheral {
};
};
reg {
reg {
name = "NIC Bandwidth Register";
name = "NIC
Current Rx
Bandwidth Register";
prefix = "BW";
prefix = "
RX
BW";
field {
field {
name = "Bytes-per-second";
name = "Bytes-per-second";
type = SLV;
type = SLV;
...
@@ -166,14 +166,14 @@ top = peripheral {
...
@@ -166,14 +166,14 @@ top = peripheral {
};
};
reg {
reg {
name = "NIC
Random
Register";
name = "NIC
Max Rx Bandwidth
Register";
prefix = "
RND
";
prefix = "
MAXRXBW
";
field {
field {
name = "
32-bit random number for throttling
";
name = "
KBytes-per-second
";
type = SLV;
type = SLV;
size =
32
;
size =
16
;
access_bus = READ_
ONLY
;
access_bus = READ_
WRITE
;
access_dev =
WRITE_ONLY
;
access_dev =
READ_WRITE
;
load = LOAD_EXT;
load = LOAD_EXT;
};
};
};
};
...
...
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