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Commit c2abae67 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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hdl: platform: added USEDW port to async fifo

parent 7b0f741e
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Showing with 82 additions and 67 deletions
generic_async_fifo_2stage.vhd
View file @ c2abae67
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-16
-- Last update: 2010-10-28
-- Last update: 2010-12-07
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -31,7 +31,8 @@ entity generic_async_fifo_2stage is
g_width : natural := 8;
g_depth : natural := 32;
g_almostfull_bit_threshold : natural := 3;
g_show_ahead : boolean := false
g_show_ahead : boolean := false;
g_with_usedw_ports : boolean := false
);
......@@ -46,7 +47,9 @@ entity generic_async_fifo_2stage is
q_o : out std_logic_vector (g_width-1 downto 0);
rd_empty_o : out std_logic;
wr_full_o : out std_logic;
almost_full_o : out std_logic
almost_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(31 downto 0);
rd_usedw_o : out std_logic_vector(31 downto 0)
);
end generic_async_fifo_2stage;
......@@ -97,7 +100,8 @@ architecture SYN of generic_async_fifo_2stage is
q : out std_logic_vector (g_width-1 downto 0);
wrreq : in std_logic;
data : in std_logic_vector (g_width-1 downto 0);
wrusedw : out std_logic_vector (log2(g_depth)-1 downto 0)
wrusedw : out std_logic_vector (log2(g_depth)-1 downto 0);
rdusedw : out std_logic_vector (log2(g_depth)-1 downto 0)
);
end component;
......@@ -109,69 +113,72 @@ begin
q_o <= sub_wire2(g_width-1 downto 0);
gen_with_showahead: if(g_show_ahead = true) generate
dcfifo_component : dcfifo -- 3stage
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => g_depth,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => g_width,
lpm_widthu => log2(g_depth),
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 5
)
port map (
wrclk => wr_clk_i,
rdreq => rd_req_i,
aclr => clear_i,
rdclk => rd_clk_i,
wrreq => wr_req_i,
data => d_i,
rdempty => sub_wire0,
wrfull => sub_wire1,
q => sub_wire2,
wrusedw => words_used
);
gen_with_showahead : if(g_show_ahead = true) generate
dcfifo_component : dcfifo -- 3stage
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => g_depth,
lpm_showahead => "ON",
lpm_type => "dcfifo",
lpm_width => g_width,
lpm_widthu => log2(g_depth),
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 5
)
port map (
wrclk => wr_clk_i,
rdreq => rd_req_i,
aclr => clear_i,
rdclk => rd_clk_i,
wrreq => wr_req_i,
data => d_i,
rdempty => sub_wire0,
wrfull => sub_wire1,
q => sub_wire2,
wrusedw => words_used,
rdusedw => rd_usedw_o(log2(g_depth)-1 downto 0)
);
end generate gen_with_showahead;
gen_no_showahead: if(g_show_ahead = false) generate
dcfifo_component : dcfifo -- 3stage
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => g_depth,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => g_width,
lpm_widthu => log2(g_depth),
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 5
)
port map (
wrclk => wr_clk_i,
rdreq => rd_req_i,
aclr => clear_i,
rdclk => rd_clk_i,
wrreq => wr_req_i,
data => d_i,
rdempty => sub_wire0,
wrfull => sub_wire1,
q => sub_wire2,
wrusedw => words_used
);
gen_no_showahead : if(g_show_ahead = false) generate
dcfifo_component : dcfifo -- 3stage
generic map (
intended_device_family => "Cyclone III",
lpm_numwords => g_depth,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => g_width,
lpm_widthu => log2(g_depth),
overflow_checking => "ON",
rdsync_delaypipe => 5,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "ON",
wrsync_delaypipe => 5
)
port map (
wrclk => wr_clk_i,
rdreq => rd_req_i,
aclr => clear_i,
rdclk => rd_clk_i,
wrreq => wr_req_i,
data => d_i,
rdempty => sub_wire0,
wrfull => sub_wire1,
q => sub_wire2,
wrusedw => words_used,
rdusedw => rd_usedw_o(log2(g_depth)-1 downto 0)
);
end generate gen_no_showahead;
almost_full_check : process (wr_clk_i, clear_i)
begin -- process almost_full_check
......@@ -188,5 +195,10 @@ begin
wr_usedw_o(log2(g_depth)-1 downto 0) <= words_used;
wr_usedw_o(wr_usedw_o'high downto log2(g_depth)) <= (others => '0');
rd_usedw_o(rd_usedw_o'high downto log2(g_depth)) <= (others => '0');
end SYN;
platform_specific.vhd
View file @ c2abae67
......@@ -12,12 +12,14 @@ package platform_specific is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
component generic_async_fifo_2stage
generic (
g_width : natural;
g_depth : natural;
g_almostfull_bit_threshold : natural;
g_show_ahead : boolean := false);
g_show_ahead : boolean := false;
g_with_usedw_ports : boolean := false);
port (
clear_i : in std_logic := '0';
d_i : in std_logic_vector (g_width-1 downto 0);
......@@ -28,9 +30,10 @@ package platform_specific is
q_o : out std_logic_vector (g_width-1 downto 0);
rd_empty_o : out std_logic;
wr_full_o : out std_logic;
almost_full_o : out std_logic);
almost_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(31 downto 0);
rd_usedw_o : out std_logic_vector(31 downto 0));
end component;
component generic_sync_fifo
generic (
......
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