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White Rabbit Switch - Gateware
Commit bac2704e authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore: improvements in input block

parent 8a53c33d
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Showing with 174 additions and 465 deletions
swc_core.vhd
View file @ bac2704e
......@@ -131,7 +131,7 @@ architecture rtl of swc_core is
-- Multiport Memory -> Input Block
signal mpm_pageend : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal mpm_full : std_logic_vector(c_swc_num_ports - 1 downto 0);
signal mpm_wr_sync : std_logic_vector(c_swc_num_ports - 1 downto 0);
----------------------------------------------------------------------------------------------------
-- signals connecting >>Input Block<< with >>Pck Transfer Arbiter<<
----------------------------------------------------------------------------------------------------
......@@ -305,6 +305,7 @@ architecture rtl of swc_core is
mpm_drdy_o => ib_drdy(i),
mpm_full_i => mpm_full(i),
mpm_flush_o => ib_flush(i),
mpm_wr_sync_i => mpm_wr_sync(i),
-------------------------------------------------------------------------------
-- I/F with Page Transfer Arbiter (PTA)
-------------------------------------------------------------------------------
......@@ -472,6 +473,7 @@ architecture rtl of swc_core is
wr_drdy_i => ib_drdy,
wr_full_o => mpm_full,
wr_flush_i => ib_flush,
wr_sync_o => mpm_wr_sync,
-------------------------------------------------------------------------------
-- I/F with Output Block
-------------------------------------------------------------------------------
......
swc_input_block.vhd
View file @ bac2704e
This diff is collapsed.
swc_output_block.vhd
View file @ bac2704e
......@@ -147,10 +147,11 @@ architecture behavoural of swc_output_block is
signal wr_array : t_addr_array;
signal rd_array : t_addr_array;
type t_state is (IDLE, SET_PAGE, READ_MPM, PAUSE_BY_SRC, PAUSE_BY_SINK, READ_LAST_WORD,WAIT_FREE_PCK, WAIT_DREQ, TABORT);
type t_state is (IDLE, SET_PAGE, RE_SET_PAGE, READ_MPM, PAUSE_BY_SRC, PAUSE_BY_SINK, READ_LAST_WORD,WAIT_FREE_PCK, WAIT_DREQ, TABORT);
signal state : t_state;
signal pgreq : std_logic;
signal re_pgreq : std_logic;
signal wr_data : std_logic_vector(c_swc_max_pck_size_width + c_swc_page_addr_width - 1 downto 0);
signal rd_data : std_logic_vector(c_swc_max_pck_size_width + c_swc_page_addr_width - 1 downto 0);
......@@ -321,7 +322,7 @@ begin -- behavoural
-- if(rx_eof_p1 = '1' or ) then
if(state = SET_PAGE) then
if(state = SET_PAGE or state = RE_SET_PAGE) then
cnt_pck_size <= (others =>'0');
cnt_one_but_last_word <= '0';
......@@ -370,6 +371,7 @@ begin -- behavoural
rx_data <= (others =>'0');
rx_eof_p1 <= '0';
rx_bytesel <= '0';
re_pgreq <= '0';
else
......@@ -408,8 +410,7 @@ begin -- behavoural
rx_sof_p1 <= '1';
rx_ctrl <= (others =>'0');
rx_data <= (others =>'0');
-- current_pck_size <= rd_pck_size;
-- pck_start_pgaddr <= rd_data(c_swc_page_addr_width - 1 downto 0);
end if;
......@@ -418,31 +419,22 @@ begin -- behavoural
rx_sof_p1 <= '0';
pgreq <= '1';
dreq <= '1';
-- current_pck_size <= rd_pck_size;
-- pck_start_pgaddr <= rd_data(c_swc_page_addr_width - 1 downto 0);
if(rx_dreq_i = '0' and mpm_drdy_i = '1') then
rx_valid <= '0';
state <= PAUSE_BY_SINK;
rx_ctrl <= mpm_ctrl_i;
rx_data <= mpm_data_i;
elsif(rx_dreq_i = '1' and mpm_drdy_i = '0') then
state <= PAUSE_BY_SRC;
rx_ctrl <= (others =>'0');
rx_data <= (others =>'0');
when RE_SET_PAGE =>
rx_sof_p1 <= '0';
re_pgreq <= '1';
dreq <= '1';
rx_valid <= '0';
state <= PAUSE_BY_SRC;
rx_ctrl <= (others =>'0');
rx_data <= (others =>'0');
else
state <= READ_MPM;
rx_valid <= '1';
rx_ctrl <= mpm_ctrl_i;
rx_data <= mpm_data_i;
end if;
rx_data <= (others =>'0');
when PAUSE_BY_SINK =>
......@@ -452,7 +444,7 @@ begin -- behavoural
-- if(rx_dreq_i = '1' and mpm_drdy_i = '1') then
if(rx_tabort_p1_i = '1' and rx_dreq_i = '1') then
state <= SET_PAGE;
state <= RE_SET_PAGE;
dreq <= '0';
rx_sof_p1 <= '1';
rx_valid <= '0';
......@@ -511,6 +503,9 @@ begin -- behavoural
if(cnt_one_but_last_word = '1') then
state <= READ_MPM;
elsif(cnt_last_word = '1') then
rx_eof_p1 <= '1';
state <= READ_LAST_WORD;
......@@ -524,12 +519,12 @@ begin -- behavoural
when PAUSE_BY_SRC =>
pgreq <= '0';
re_pgreq <= '0';
-- if(rx_dreq_i = '1' and mpm_drdy_i = '1') then
if(rx_tabort_p1_i = '1' and rx_dreq_i = '1') then
state <= SET_PAGE;
state <= RE_SET_PAGE;
dreq <= '0';
rx_sof_p1 <= '1';
rx_valid <= '0';
......@@ -609,7 +604,7 @@ begin -- behavoural
if(rx_tabort_p1_i = '1' and rx_dreq_i = '1') then
state <= SET_PAGE;
state <= RE_SET_PAGE;
dreq <= '0';
rx_sof_p1 <= '1';
rx_valid <= '0';
......@@ -755,7 +750,7 @@ begin -- behavoural
if(rx_dreq_i = '1') then
state <= SET_PAGE;
state <= RE_SET_PAGE;
rx_sof_p1 <= '1';
rx_ctrl <= (others =>'0');
......@@ -825,7 +820,7 @@ begin -- behavoural
rd_pck_size <= rd_data(c_swc_max_pck_size_width + c_swc_page_addr_width - 1 downto c_swc_page_addr_width);
mpm_pgreq_o <= pgreq;
mpm_pgreq_o <= pgreq or re_pgreq;
-- IMPORTANT : a trick needed here, to make things faster, we provide pgaddr straight
......
swc_packet_mem.vhd
View file @ bac2704e
......@@ -125,6 +125,8 @@ entity swc_packet_mem is
-- request to write the content of pump's input register to FB SRAM memory,
-- thus flash/clean input register of the pump
wr_flush_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
wr_sync_o : out std_logic_vector(c_swc_num_ports -1 downto 0);
------------------- reading from the shared memory --------------------------
-- indicates that a port X wants to write page address of the "read" access
......@@ -595,5 +597,5 @@ begin -- rtl
ll_write_done_o <= write_done_i;
llist_rd_data <= data_i ;
wr_sync_o <= sync_sreg(c_swc_num_ports-1 downto 0);
end rtl;
swc_packet_mem_write_pump.vhd
View file @ bac2704e
......@@ -850,28 +850,16 @@ begin -- rtl
ll_idle <= '1' when (state = IDLE) else '0';
we_o <= we_int;
full_o <= (((reg_full -- obvous
or
--==== needs test - start ===
(cnt_last_word and drdy_i)
or
(nasty_wait_full and drdy_i))
--==== needs test - end ===
-- (cnt_last_word)) -- we need to set full in advance when the last word is not on sync
-- (this means that we need full to stop writing and wait for synchronization
-- with sync
-- or
-- pgend
-- ) -- in case when new page is not set by the end of the last "word" of the page
-- we need to wait for the page to be allocated - in such case we need to stop
-- and here, again, we need to set full_o in advance by making the (X and not sync_i)
-- trick
and
(not sync_i)) or(pgend and sync_i));-- or (sync_i and (not drdy_i)));-- and not before_sync;
full_o <= reg_full;
--
-- (((reg_full -- obvous
-- or
-- (cnt_last_word and drdy_i)
-- or
-- (nasty_wait_full and drdy_i))
-- and
-- (not sync_i)) or(pgend and sync_i));-- or (sync_i and (not drdy_i)));-- and not before_sync;
-- FIXME: investigate this solutions
--work here
--addr_o <= pgaddr_i & zeros (c_swc_page_offset_width-1 downto 0) when (we_int = '1' and pgreq_i = '1') else mem_addr;
addr_o <= mem_addr;
......
swc_swcore_pkg.vhd
View file @ bac2704e
......@@ -63,6 +63,10 @@ package swc_swcore_pkg is
--
constant c_swc_input_fifo_size : integer := 2 * c_swc_packet_mem_multiply;
constant c_swc_input_fifo_size_log2 : integer := integer(CEIL(LOG2(real(c_swc_input_fifo_size - 1))));
constant c_swc_fifo_full_in_advance : integer := c_swc_input_fifo_size - 3;
constant c_swc_num_ports_width : integer := integer(CEIL(LOG2(real(c_swc_num_ports-1))));
constant c_swc_packet_mem_num_pages : integer := (c_swc_packet_mem_size / c_swc_page_size); -- 65536/64 = 1024
......@@ -258,7 +262,8 @@ package swc_swcore_pkg is
mpm_ctrl_o : out std_logic_vector(c_swc_ctrl_width - 1 downto 0);
mpm_drdy_o : out std_logic;
mpm_full_i : in std_logic;
mpm_flush_o : out std_logic;
mpm_flush_o : out std_logic;
mpm_wr_sync_i : in std_logic;
-------------------------------------------------------------------------------
-- I/F with Page Transfer Arbiter (PTA)
-------------------------------------------------------------------------------
......@@ -309,6 +314,7 @@ package swc_swcore_pkg is
wr_drdy_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
wr_full_o : out std_logic_vector(c_swc_num_ports-1 downto 0);
wr_flush_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
wr_sync_o : out std_logic_vector(c_swc_num_ports -1 downto 0);
------------------- reading from the shared memory --------------------------
rd_pagereq_i : in std_logic_vector(c_swc_num_ports-1 downto 0);
rd_pageaddr_i : in std_logic_vector(c_swc_num_ports * c_swc_page_addr_width - 1 downto 0);
......
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