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White Rabbit Switch - Gateware
Commit b6be79f8 authored by Maciej Lipinski's avatar Maciej Lipinski
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RTU: modified the WB interface of RTU to extend the number of ports supported by… 

RTU: modified the WB interface of RTU to extend the number of ports supported by rtu (it was up to 10). Now, WB-wise RTU supports 20 ports (however, there are other limitations which make the current max number of ports = 16)
parent eca97109
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Showing with 2911 additions and 28 deletions
modules/wrsw_rtu/Manifest.py
View file @ b6be79f8
......@@ -6,7 +6,8 @@ files = [
"wrsw_rtu_crc_pkg.vhd",
"wrsw_rtu_match.vhd",
"wrsw_rtu_private_pkg.vhd",
"wrsw_rtu_wb.vhd",
#"wrsw_rtu_wb.vhd",
"wrsw_rtu_wb_20ports.vhd",
"PCK_CRC16_D16.vhd",
"showahead_fifo.vhd",
"wrsw_rtu_components_pkg.vhd",
......
modules/wrsw_rtu/wrsw_rtu.vhd
View file @ b6be79f8
......@@ -303,12 +303,12 @@ architecture behavioral of wrsw_rtu is
signal gcr_mfifotrig_in : std_logic;
signal gcr_mfifotrig_load : std_logic;
signal s_pcr_learn_en : std_logic_vector(c_rtu_num_ports - 1 downto 0);
signal s_pcr_pass_all : std_logic_vector(c_rtu_num_ports - 1 downto 0);
signal s_pcr_pass_bpdu : std_logic_vector(c_rtu_num_ports - 1 downto 0);
signal s_pcr_fix_prio : std_logic_vector(c_rtu_num_ports - 1 downto 0);
signal s_pcr_prio_val : std_logic_vector(c_wrsw_prio_width * c_rtu_num_ports - 1 downto 0);
signal s_pcr_b_unrec : std_logic_vector(c_rtu_num_ports - 1 downto 0);
signal s_pcr_learn_en : std_logic_vector(c_wrsw_num_ports_max - 1 downto 0);
signal s_pcr_pass_all : std_logic_vector(c_wrsw_num_ports_max - 1 downto 0);
signal s_pcr_pass_bpdu : std_logic_vector(c_wrsw_num_ports_max - 1 downto 0);
signal s_pcr_fix_prio : std_logic_vector(c_wrsw_num_ports_max - 1 downto 0);
signal s_pcr_prio_val : std_logic_vector(c_wrsw_num_ports_max * c_rtu_num_ports - 1 downto 0);
signal s_pcr_b_unrec : std_logic_vector(c_wrsw_num_ports_max - 1 downto 0);
--| RESPONSE FIFO
......@@ -557,10 +557,10 @@ begin
rtu_vlan_tab_data_i => s_vlan_tab_data,
rtu_vlan_tab_rd_o => s_vlan_tab_rd,
rtu_gcr_g_ena_i => s_global_ena,
rtu_pcr_pass_all_i => s_pcr_pass_all,
rtu_pcr_learn_en_i => s_pcr_learn_en,
rtu_pcr_pass_bpdu_i => s_pcr_pass_bpdu,
rtu_pcr_b_unrec_i => s_pcr_b_unrec,
rtu_pcr_pass_all_i => s_pcr_pass_all(c_rtu_num_ports - 1 downto 0),
rtu_pcr_learn_en_i => s_pcr_learn_en(c_rtu_num_ports - 1 downto 0),
rtu_pcr_pass_bpdu_i => s_pcr_pass_bpdu(c_rtu_num_ports - 1 downto 0),
rtu_pcr_b_unrec_i => s_pcr_b_unrec(c_rtu_num_ports - 1 downto 0),
rtu_crc_poly_i => s_rtu_gcr_poly_used --x"1021"-- x"0589" -- x"8005" --x"1021" --x"8005", --
-- rtu_rw_bank_i => s_vlan_bsel
);
......@@ -721,7 +721,80 @@ begin
rtu_pcr9_pass_bpdu_o => s_pcr_pass_bpdu(9),
rtu_pcr9_fix_prio_o => s_pcr_fix_prio(9),
rtu_pcr9_prio_val_o => s_pcr_prio_val(3*9 + 3 - 1 downto 3*9),
rtu_pcr9_b_unrec_o => s_pcr_b_unrec(9)
rtu_pcr9_b_unrec_o => s_pcr_b_unrec(9),
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
rtu_pcr10_learn_en_o => s_pcr_learn_en(10),
rtu_pcr10_pass_all_o => s_pcr_pass_all(10),
rtu_pcr10_pass_bpdu_o => s_pcr_pass_bpdu(10),
rtu_pcr10_fix_prio_o => s_pcr_fix_prio(10),
rtu_pcr10_prio_val_o => s_pcr_prio_val(3*10 + 3 - 1 downto 3*10),
rtu_pcr10_b_unrec_o => s_pcr_b_unrec(10),
rtu_pcr11_learn_en_o => s_pcr_learn_en(11),
rtu_pcr11_pass_all_o => s_pcr_pass_all(11),
rtu_pcr11_pass_bpdu_o => s_pcr_pass_bpdu(11),
rtu_pcr11_fix_prio_o => s_pcr_fix_prio(11),
rtu_pcr11_prio_val_o => s_pcr_prio_val(3*11 + 3 - 1 downto 3*11),
rtu_pcr11_b_unrec_o => s_pcr_b_unrec(11),
rtu_pcr12_learn_en_o => s_pcr_learn_en(12),
rtu_pcr12_pass_all_o => s_pcr_pass_all(12),
rtu_pcr12_pass_bpdu_o => s_pcr_pass_bpdu(12),
rtu_pcr12_fix_prio_o => s_pcr_fix_prio(12),
rtu_pcr12_prio_val_o => s_pcr_prio_val(3*12 + 3 - 1 downto 3*12),
rtu_pcr12_b_unrec_o => s_pcr_b_unrec(12),
rtu_pcr13_learn_en_o => s_pcr_learn_en(13),
rtu_pcr13_pass_all_o => s_pcr_pass_all(13),
rtu_pcr13_pass_bpdu_o => s_pcr_pass_bpdu(13),
rtu_pcr13_fix_prio_o => s_pcr_fix_prio(13),
rtu_pcr13_prio_val_o => s_pcr_prio_val(3*13 + 3 - 1 downto 3*13),
rtu_pcr13_b_unrec_o => s_pcr_b_unrec(13),
rtu_pcr14_learn_en_o => s_pcr_learn_en(14),
rtu_pcr14_pass_all_o => s_pcr_pass_all(14),
rtu_pcr14_pass_bpdu_o => s_pcr_pass_bpdu(14),
rtu_pcr14_fix_prio_o => s_pcr_fix_prio(14),
rtu_pcr14_prio_val_o => s_pcr_prio_val(3*14 + 3 - 1 downto 3*14),
rtu_pcr14_b_unrec_o => s_pcr_b_unrec(14),
rtu_pcr15_learn_en_o => s_pcr_learn_en(15),
rtu_pcr15_pass_all_o => s_pcr_pass_all(15),
rtu_pcr15_pass_bpdu_o => s_pcr_pass_bpdu(15),
rtu_pcr15_fix_prio_o => s_pcr_fix_prio(15),
rtu_pcr15_prio_val_o => s_pcr_prio_val(3*15 + 3 - 1 downto 3*15),
rtu_pcr15_b_unrec_o => s_pcr_b_unrec(15),
rtu_pcr16_learn_en_o => s_pcr_learn_en(16),
rtu_pcr16_pass_all_o => s_pcr_pass_all(16),
rtu_pcr16_pass_bpdu_o => s_pcr_pass_bpdu(16),
rtu_pcr16_fix_prio_o => s_pcr_fix_prio(16),
rtu_pcr16_prio_val_o => s_pcr_prio_val(3*16 + 3 - 1 downto 3*16),
rtu_pcr16_b_unrec_o => s_pcr_b_unrec(16),
rtu_pcr17_learn_en_o => s_pcr_learn_en(17),
rtu_pcr17_pass_all_o => s_pcr_pass_all(17),
rtu_pcr17_pass_bpdu_o => s_pcr_pass_bpdu(17),
rtu_pcr17_fix_prio_o => s_pcr_fix_prio(17),
rtu_pcr17_prio_val_o => s_pcr_prio_val(3*17 + 3 - 1 downto 3*17),
rtu_pcr17_b_unrec_o => s_pcr_b_unrec(17),
rtu_pcr18_learn_en_o => s_pcr_learn_en(18),
rtu_pcr18_pass_all_o => s_pcr_pass_all(18),
rtu_pcr18_pass_bpdu_o => s_pcr_pass_bpdu(18),
rtu_pcr18_fix_prio_o => s_pcr_fix_prio(18),
rtu_pcr18_prio_val_o => s_pcr_prio_val(3*18 + 3 - 1 downto 3*18),
rtu_pcr18_b_unrec_o => s_pcr_b_unrec(18),
rtu_pcr19_learn_en_o => s_pcr_learn_en(19),
rtu_pcr19_pass_all_o => s_pcr_pass_all(19),
rtu_pcr19_pass_bpdu_o => s_pcr_pass_bpdu(19),
rtu_pcr19_fix_prio_o => s_pcr_fix_prio(19),
rtu_pcr19_prio_val_o => s_pcr_prio_val(3*19 + 3 - 1 downto 3*19),
rtu_pcr19_b_unrec_o => s_pcr_b_unrec(19)
------------------------------------------------------------------------------------------
);
......
modules/wrsw_rtu/wrsw_rtu_private_pkg.vhd
View file @ b6be79f8
......@@ -51,12 +51,13 @@ package wrsw_rtu_private_pkg is
----------------------------------------------------------------------------------------
-- Number of switch ports (including NIC)
constant c_wrsw_num_ports : integer := 11;
constant c_wrsw_num_ports_max : integer := 20; -- need for WB I/F
constant c_wrsw_num_ports : integer := 16;
constant c_wrsw_mac_addr_width : integer := 48;
constant c_wrsw_vid_width : integer := 12;
constant c_wrsw_prio_width : integer := 3;
constant c_wrsw_prio_levels : integer := 8;
constant c_rtu_num_ports : integer := 10; --c_wrsw_num_ports - 1;
constant c_rtu_num_ports : integer := 15;--10; --c_wrsw_num_ports - 1;
constant c_wrsw_fid_width : integer := 8;
constant c_wrsw_hash_width : integer := 9;
constant c_wrsw_crc_width : integer := 16;
......@@ -308,7 +309,69 @@ package wrsw_rtu_private_pkg is
rtu_pcr9_pass_bpdu_o : out std_logic;
rtu_pcr9_fix_prio_o : out std_logic;
rtu_pcr9_prio_val_o : out std_logic_vector(2 downto 0);
rtu_pcr9_b_unrec_o : out std_logic);
rtu_pcr9_b_unrec_o : out std_logic;
rtu_pcr10_learn_en_o : out std_logic;
rtu_pcr10_pass_all_o : out std_logic;
rtu_pcr10_pass_bpdu_o : out std_logic;
rtu_pcr10_fix_prio_o : out std_logic;
rtu_pcr10_prio_val_o : out std_logic_vector(2 downto 0);
rtu_pcr10_b_unrec_o : out std_logic;
rtu_pcr11_learn_en_o : out std_logic;
rtu_pcr11_pass_all_o : out std_logic;
rtu_pcr11_pass_bpdu_o : out std_logic;
rtu_pcr11_fix_prio_o : out std_logic;
rtu_pcr11_prio_val_o : out std_logic_vector(2 downto 0);
rtu_pcr11_b_unrec_o : out std_logic;
rtu_pcr12_learn_en_o : out std_logic;
rtu_pcr12_pass_all_o : out std_logic;
rtu_pcr12_pass_bpdu_o : out std_logic;
rtu_pcr12_fix_prio_o : out std_logic;
rtu_pcr12_prio_val_o : out std_logic_vector(2 downto 0);
rtu_pcr12_b_unrec_o : out std_logic;
rtu_pcr13_learn_en_o : out std_logic;
rtu_pcr13_pass_all_o : out std_logic;
rtu_pcr13_pass_bpdu_o : out std_logic;
rtu_pcr13_fix_prio_o : out std_logic;
rtu_pcr13_prio_val_o : out std_logic_vector(2 downto 0);
rtu_pcr13_b_unrec_o : out std_logic;
rtu_pcr14_learn_en_o : out std_logic;
rtu_pcr14_pass_all_o : out std_logic;
rtu_pcr14_pass_bpdu_o : out std_logic;
rtu_pcr14_fix_prio_o : out std_logic;
rtu_pcr14_prio_val_o : out std_logic_vector(2 downto 0);
rtu_pcr14_b_unrec_o : out std_logic;
rtu_pcr15_learn_en_o : out std_logic;
rtu_pcr15_pass_all_o : out std_logic;
rtu_pcr15_pass_bpdu_o : out std_logic;
rtu_pcr15_fix_prio_o : out std_logic;
rtu_pcr15_prio_val_o : out std_logic_vector(2 downto 0);
rtu_pcr15_b_unrec_o : out std_logic;
rtu_pcr16_learn_en_o : out std_logic;
rtu_pcr16_pass_all_o : out std_logic;
rtu_pcr16_pass_bpdu_o : out std_logic;
rtu_pcr16_fix_prio_o : out std_logic;
rtu_pcr16_prio_val_o : out std_logic_vector(2 downto 0);
rtu_pcr16_b_unrec_o : out std_logic;
rtu_pcr17_learn_en_o : out std_logic;
rtu_pcr17_pass_all_o : out std_logic;
rtu_pcr17_pass_bpdu_o : out std_logic;
rtu_pcr17_fix_prio_o : out std_logic;
rtu_pcr17_prio_val_o : out std_logic_vector(2 downto 0);
rtu_pcr17_b_unrec_o : out std_logic;
rtu_pcr18_learn_en_o : out std_logic;
rtu_pcr18_pass_all_o : out std_logic;
rtu_pcr18_pass_bpdu_o : out std_logic;
rtu_pcr18_fix_prio_o : out std_logic;
rtu_pcr18_prio_val_o : out std_logic_vector(2 downto 0);
rtu_pcr18_b_unrec_o : out std_logic;
rtu_pcr19_learn_en_o : out std_logic;
rtu_pcr19_pass_all_o : out std_logic;
rtu_pcr19_pass_bpdu_o : out std_logic;
rtu_pcr19_fix_prio_o : out std_logic;
rtu_pcr19_prio_val_o : out std_logic_vector(2 downto 0);
rtu_pcr19_b_unrec_o : out std_logic
);
end component;
----------------------------------------------------------------------------------------
--| CRC-based hash calculation
......
modules/wrsw_rtu/wrsw_rtu_wb_20ports.vhd 0 → 100644
View file @ b6be79f8
This source diff could not be displayed because it is too large. You can view the blob instead.
sim/regs/rtu_regs.vh
View file @ b6be79f8
......@@ -136,31 +136,161 @@
`define RTU_PCR9_PRIO_VAL 32'h00000070
`define RTU_PCR9_B_UNREC_OFFSET 7
`define RTU_PCR9_B_UNREC 32'h00000080
`define ADDR_RTU_EIC_IDR 16'h40
`define ADDR_RTU_PCR10 16'h30
`define RTU_PCR10_LEARN_EN_OFFSET 0
`define RTU_PCR10_LEARN_EN 32'h00000001
`define RTU_PCR10_PASS_ALL_OFFSET 1
`define RTU_PCR10_PASS_ALL 32'h00000002
`define RTU_PCR10_PASS_BPDU_OFFSET 2
`define RTU_PCR10_PASS_BPDU 32'h00000004
`define RTU_PCR10_FIX_PRIO_OFFSET 3
`define RTU_PCR10_FIX_PRIO 32'h00000008
`define RTU_PCR10_PRIO_VAL_OFFSET 4
`define RTU_PCR10_PRIO_VAL 32'h00000070
`define RTU_PCR10_B_UNREC_OFFSET 7
`define RTU_PCR10_B_UNREC 32'h00000080
`define ADDR_RTU_PCR11 16'h34
`define RTU_PCR11_LEARN_EN_OFFSET 0
`define RTU_PCR11_LEARN_EN 32'h00000001
`define RTU_PCR11_PASS_ALL_OFFSET 1
`define RTU_PCR11_PASS_ALL 32'h00000002
`define RTU_PCR11_PASS_BPDU_OFFSET 2
`define RTU_PCR11_PASS_BPDU 32'h00000004
`define RTU_PCR11_FIX_PRIO_OFFSET 3
`define RTU_PCR11_FIX_PRIO 32'h00000008
`define RTU_PCR11_PRIO_VAL_OFFSET 4
`define RTU_PCR11_PRIO_VAL 32'h00000070
`define RTU_PCR11_B_UNREC_OFFSET 7
`define RTU_PCR11_B_UNREC 32'h00000080
`define ADDR_RTU_PCR12 16'h38
`define RTU_PCR12_LEARN_EN_OFFSET 0
`define RTU_PCR12_LEARN_EN 32'h00000001
`define RTU_PCR12_PASS_ALL_OFFSET 1
`define RTU_PCR12_PASS_ALL 32'h00000002
`define RTU_PCR12_PASS_BPDU_OFFSET 2
`define RTU_PCR12_PASS_BPDU 32'h00000004
`define RTU_PCR12_FIX_PRIO_OFFSET 3
`define RTU_PCR12_FIX_PRIO 32'h00000008
`define RTU_PCR12_PRIO_VAL_OFFSET 4
`define RTU_PCR12_PRIO_VAL 32'h00000070
`define RTU_PCR12_B_UNREC_OFFSET 7
`define RTU_PCR12_B_UNREC 32'h00000080
`define ADDR_RTU_PCR13 16'h3c
`define RTU_PCR13_LEARN_EN_OFFSET 0
`define RTU_PCR13_LEARN_EN 32'h00000001
`define RTU_PCR13_PASS_ALL_OFFSET 1
`define RTU_PCR13_PASS_ALL 32'h00000002
`define RTU_PCR13_PASS_BPDU_OFFSET 2
`define RTU_PCR13_PASS_BPDU 32'h00000004
`define RTU_PCR13_FIX_PRIO_OFFSET 3
`define RTU_PCR13_FIX_PRIO 32'h00000008
`define RTU_PCR13_PRIO_VAL_OFFSET 4
`define RTU_PCR13_PRIO_VAL 32'h00000070
`define RTU_PCR13_B_UNREC_OFFSET 7
`define RTU_PCR13_B_UNREC 32'h00000080
`define ADDR_RTU_PCR14 16'h40
`define RTU_PCR14_LEARN_EN_OFFSET 0
`define RTU_PCR14_LEARN_EN 32'h00000001
`define RTU_PCR14_PASS_ALL_OFFSET 1
`define RTU_PCR14_PASS_ALL 32'h00000002
`define RTU_PCR14_PASS_BPDU_OFFSET 2
`define RTU_PCR14_PASS_BPDU 32'h00000004
`define RTU_PCR14_FIX_PRIO_OFFSET 3
`define RTU_PCR14_FIX_PRIO 32'h00000008
`define RTU_PCR14_PRIO_VAL_OFFSET 4
`define RTU_PCR14_PRIO_VAL 32'h00000070
`define RTU_PCR14_B_UNREC_OFFSET 7
`define RTU_PCR14_B_UNREC 32'h00000080
`define ADDR_RTU_PCR15 16'h44
`define RTU_PCR15_LEARN_EN_OFFSET 0
`define RTU_PCR15_LEARN_EN 32'h00000001
`define RTU_PCR15_PASS_ALL_OFFSET 1
`define RTU_PCR15_PASS_ALL 32'h00000002
`define RTU_PCR15_PASS_BPDU_OFFSET 2
`define RTU_PCR15_PASS_BPDU 32'h00000004
`define RTU_PCR15_FIX_PRIO_OFFSET 3
`define RTU_PCR15_FIX_PRIO 32'h00000008
`define RTU_PCR15_PRIO_VAL_OFFSET 4
`define RTU_PCR15_PRIO_VAL 32'h00000070
`define RTU_PCR15_B_UNREC_OFFSET 7
`define RTU_PCR15_B_UNREC 32'h00000080
`define ADDR_RTU_PCR16 16'h48
`define RTU_PCR16_LEARN_EN_OFFSET 0
`define RTU_PCR16_LEARN_EN 32'h00000001
`define RTU_PCR16_PASS_ALL_OFFSET 1
`define RTU_PCR16_PASS_ALL 32'h00000002
`define RTU_PCR16_PASS_BPDU_OFFSET 2
`define RTU_PCR16_PASS_BPDU 32'h00000004
`define RTU_PCR16_FIX_PRIO_OFFSET 3
`define RTU_PCR16_FIX_PRIO 32'h00000008
`define RTU_PCR16_PRIO_VAL_OFFSET 4
`define RTU_PCR16_PRIO_VAL 32'h00000070
`define RTU_PCR16_B_UNREC_OFFSET 7
`define RTU_PCR16_B_UNREC 32'h00000080
`define ADDR_RTU_PCR17 16'h4c
`define RTU_PCR17_LEARN_EN_OFFSET 0
`define RTU_PCR17_LEARN_EN 32'h00000001
`define RTU_PCR17_PASS_ALL_OFFSET 1
`define RTU_PCR17_PASS_ALL 32'h00000002
`define RTU_PCR17_PASS_BPDU_OFFSET 2
`define RTU_PCR17_PASS_BPDU 32'h00000004
`define RTU_PCR17_FIX_PRIO_OFFSET 3
`define RTU_PCR17_FIX_PRIO 32'h00000008
`define RTU_PCR17_PRIO_VAL_OFFSET 4
`define RTU_PCR17_PRIO_VAL 32'h00000070
`define RTU_PCR17_B_UNREC_OFFSET 7
`define RTU_PCR17_B_UNREC 32'h00000080
`define ADDR_RTU_PCR18 16'h50
`define RTU_PCR18_LEARN_EN_OFFSET 0
`define RTU_PCR18_LEARN_EN 32'h00000001
`define RTU_PCR18_PASS_ALL_OFFSET 1
`define RTU_PCR18_PASS_ALL 32'h00000002
`define RTU_PCR18_PASS_BPDU_OFFSET 2
`define RTU_PCR18_PASS_BPDU 32'h00000004
`define RTU_PCR18_FIX_PRIO_OFFSET 3
`define RTU_PCR18_FIX_PRIO 32'h00000008
`define RTU_PCR18_PRIO_VAL_OFFSET 4
`define RTU_PCR18_PRIO_VAL 32'h00000070
`define RTU_PCR18_B_UNREC_OFFSET 7
`define RTU_PCR18_B_UNREC 32'h00000080
`define ADDR_RTU_PCR19 16'h54
`define RTU_PCR19_LEARN_EN_OFFSET 0
`define RTU_PCR19_LEARN_EN 32'h00000001
`define RTU_PCR19_PASS_ALL_OFFSET 1
`define RTU_PCR19_PASS_ALL 32'h00000002
`define RTU_PCR19_PASS_BPDU_OFFSET 2
`define RTU_PCR19_PASS_BPDU 32'h00000004
`define RTU_PCR19_FIX_PRIO_OFFSET 3
`define RTU_PCR19_FIX_PRIO 32'h00000008
`define RTU_PCR19_PRIO_VAL_OFFSET 4
`define RTU_PCR19_PRIO_VAL 32'h00000070
`define RTU_PCR19_B_UNREC_OFFSET 7
`define RTU_PCR19_B_UNREC 32'h00000080
`define ADDR_RTU_EIC_IDR 16'h60
`define RTU_EIC_IDR_NEMPTY_OFFSET 0
`define RTU_EIC_IDR_NEMPTY 32'h00000001
`define ADDR_RTU_EIC_IER 16'h44
`define ADDR_RTU_EIC_IER 16'h64
`define RTU_EIC_IER_NEMPTY_OFFSET 0
`define RTU_EIC_IER_NEMPTY 32'h00000001
`define ADDR_RTU_EIC_IMR 16'h48
`define ADDR_RTU_EIC_IMR 16'h68
`define RTU_EIC_IMR_NEMPTY_OFFSET 0
`define RTU_EIC_IMR_NEMPTY 32'h00000001
`define ADDR_RTU_EIC_ISR 16'h4c
`define ADDR_RTU_EIC_ISR 16'h6c
`define RTU_EIC_ISR_NEMPTY_OFFSET 0
`define RTU_EIC_ISR_NEMPTY 32'h00000001
`define ADDR_RTU_UFIFO_R0 16'h50
`define ADDR_RTU_UFIFO_R0 16'h70
`define RTU_UFIFO_R0_DMAC_LO_OFFSET 0
`define RTU_UFIFO_R0_DMAC_LO 32'hffffffff
`define ADDR_RTU_UFIFO_R1 16'h54
`define ADDR_RTU_UFIFO_R1 16'h74
`define RTU_UFIFO_R1_DMAC_HI_OFFSET 0
`define RTU_UFIFO_R1_DMAC_HI 32'h0000ffff
`define ADDR_RTU_UFIFO_R2 16'h58
`define ADDR_RTU_UFIFO_R2 16'h78
`define RTU_UFIFO_R2_SMAC_LO_OFFSET 0
`define RTU_UFIFO_R2_SMAC_LO 32'hffffffff
`define ADDR_RTU_UFIFO_R3 16'h5c
`define ADDR_RTU_UFIFO_R3 16'h7c
`define RTU_UFIFO_R3_SMAC_HI_OFFSET 0
`define RTU_UFIFO_R3_SMAC_HI 32'h0000ffff
`define ADDR_RTU_UFIFO_R4 16'h60
`define ADDR_RTU_UFIFO_R4 16'h80
`define RTU_UFIFO_R4_VID_OFFSET 0
`define RTU_UFIFO_R4_VID 32'h00000fff
`define RTU_UFIFO_R4_PRIO_OFFSET 12
......@@ -171,18 +301,18 @@
`define RTU_UFIFO_R4_HAS_VID 32'h00100000
`define RTU_UFIFO_R4_HAS_PRIO_OFFSET 21
`define RTU_UFIFO_R4_HAS_PRIO 32'h00200000
`define ADDR_RTU_UFIFO_CSR 16'h64
`define ADDR_RTU_UFIFO_CSR 16'h84
`define RTU_UFIFO_CSR_EMPTY_OFFSET 17
`define RTU_UFIFO_CSR_EMPTY 32'h00020000
`define RTU_UFIFO_CSR_USEDW_OFFSET 0
`define RTU_UFIFO_CSR_USEDW 32'h0000007f
`define ADDR_RTU_MFIFO_R0 16'h68
`define ADDR_RTU_MFIFO_R0 16'h88
`define RTU_MFIFO_R0_AD_SEL_OFFSET 0
`define RTU_MFIFO_R0_AD_SEL 32'h00000001
`define ADDR_RTU_MFIFO_R1 16'h6c
`define ADDR_RTU_MFIFO_R1 16'h8c
`define RTU_MFIFO_R1_AD_VAL_OFFSET 0
`define RTU_MFIFO_R1_AD_VAL 32'hffffffff
`define ADDR_RTU_MFIFO_CSR 16'h70
`define ADDR_RTU_MFIFO_CSR 16'h90
`define RTU_MFIFO_CSR_FULL_OFFSET 16
`define RTU_MFIFO_CSR_FULL 32'h00010000
`define RTU_MFIFO_CSR_EMPTY_OFFSET 17
......
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