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White Rabbit Switch - Gateware
Commit af344aa3 authored by Maciej Lipinski's avatar Maciej Lipinski
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LJ: improve/generalize Low-Jitter functionality detection/handling (WIP)

parent a155acb2
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    modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
    View file @ af344aa3
    ......@@ -138,7 +138,8 @@ entity wrsw_rt_subsystem is
    lj_clk2_en : out std_logic;
    lj_detected_o : out std_logic;
    lj_osc_freq_i : in std_logic_vector (2 downto 0) := (others=>'0');
    -- LJD AD9516
    lj_periph_id_i: in std_logic_vector (2 downto 0) := (others=>'0');
    -- LJD AD9516 -- below IOs used when lj_detected_o = '1'
    lj_pll_mosi_o : out std_logic;
    lj_pll_miso_i : in std_logic;
    lj_pll_sck_o : out std_logic;
    ......@@ -182,7 +183,7 @@ architecture rtl of wrsw_rt_subsystem is
    -- 0x10300 - 0x10400: GPIO
    -- 0x10400 - 0x10500: Timer
    constant c_NUM_GPIO_PINS : integer := 9;
    constant c_NUM_GPIO_PINS : integer := 11;
    constant c_NUM_WB_SLAVES : integer := 9;
    constant c_MASTER_CPU : integer := 0;
    ......@@ -487,6 +488,7 @@ begin -- rtl
    gpio_in(4) <= lj_board_detected;
    gpio_in(7 downto 5) <= lj_osc_freq_i;
    gpio_in(10 downto 8)<= lj_periph_id_i;
    U_Main_DAC : gc_serial_dac
    ......
    top/bare_top/scb_top_bare.vhd
    View file @ af344aa3
    ......@@ -144,9 +144,10 @@ entity scb_top_bare is
    lj_loopback_o : out std_logic;
    lj_clk1_en : out std_logic;
    lj_clk2_en : out std_logic;
    lj_detected_o : out std_logic;
    lj_present_o : out std_logic;
    lj_ext_gm_pll_pres_o : out std_logic; -- '1' when GM's external PLL present
    lj_ext_gm_clk_diff_o : out std_logic; -- '1' when differencial ext 10MHz sinput used
    lj_osc_freq_i : in std_logic_vector (2 downto 0);
    lj_periph_id_i : in std_logic_vector (2 downto 0);
    -- LJD AD9516
    lj_pll_mosi_o : out std_logic;
    lj_pll_miso_i : in std_logic;
    ......@@ -159,6 +160,10 @@ entity scb_top_bare is
    -------------------------------------------------------------------------------
    -- Misc pins
    -------------------------------------------------------------------------------
    -- External counter
    wd_int_i : in std_logic;
    wd_scl_i : in std_logic;
    wd_sda_b : inout std_logic;
    -- GTX clock fanout enable
    clk_en_o : out std_logic;
    ......@@ -467,8 +472,8 @@ architecture rtl of scb_top_bare is
    signal nic_rtu_rsp : t_rtu_response;
    signal nic_rtu_ack : std_logic;
    signal lj_present : std_logic;
    signal lj_detected : std_logic;
    signal lj_ext_gm_clk_diff : std_logic;
    signal lj_ext_gm_pll_pres : std_logic;
    signal dac_main_sync_n : std_logic;
    signal dac_main_sclk : std_logic;
    signal dac_main_data : std_logic;
    ......@@ -677,6 +682,8 @@ begin
    lj_clk2_en => lj_clk2_en,
    lj_detected_o => lj_detected,
    lj_osc_freq_i => lj_osc_freq_i,
    lj_periph_id_i => lj_periph_id_i,
    -- below IOs used when lj_detected_o = '1'
    lj_pll_mosi_o => lj_pll_mosi_o,
    lj_pll_miso_i => lj_pll_miso_i,
    lj_pll_sck_o => lj_pll_sck_o,
    ......@@ -1332,14 +1339,80 @@ begin
    end generate;
    -------------------------------------------------------------------------------
    -- WRS Low jitter daughterboard
    -- WRS Low jitter support MUX
    -------------------------------------------------------------------------------
    --
    LJ_perip_select : process (lj_detected, ljd_osc_freq_i, lj_periph_id_i,
    dac_main_sync_n, dac_main_sclk, dac_main_data)
    begin
    --------------------------------------------------------------------------
    -- no Low-Jitter functionality at all, default clocking connections
    --------------------------------------------------------------------------
    if (lj_detected = '0') then
    dac_main_sync_n_o <= dac_main_sync_n;
    dac_main_sclk_o <= dac_main_sclk;
    dac_main_data_o <= dac_main_data;
    lj_dac_main_sync_n_o <= '0';
    lj_dac_main_sclk_o <= '0';
    lj_dac_main_data_o <= '0';
    lj_ext_gm_pll_pres_o <= '0';
    lj_ext_gm_clk_diff_o <= '0';
    --------------------------------------------------------------------------
    -- SyncTech WRS-FL with low-jitter capability integrated into main board
    -- Versions supported: WRS-FL v1.0 and v1.5
    --------------------------------------------------------------------------
    elsif (lj_osc_freq_i = "111" and lj_periph_id_i = "111" ) then
    dac_main_sync_n_o <= dac_main_sync_n;
    dac_main_sclk_o <= dac_main_sclk;
    dac_main_data_o <= dac_main_data;
    lj_dac_main_sync_n_o <= '0';
    lj_dac_main_sclk_o <= '0';
    lj_dac_main_data_o <= '0';
    lj_ext_gm_pll_pres_o <= '1';
    lj_ext_gm_clk_diff_o <= '0';
    -- If possible, do the distinction below:
    if (FPGA_WD_INT = '1' ) then -- WRS-LJ v1.0
    -- HDL for AD5662
    else then -- WRS-LJ v1.5
    -- HDL for AD5683R
    end if;
    elsif (ljd_osc_freq_i = "111" and lj_periph_id_i = "110") then
    --------------------------------------------------------------------------
    -- Safran WRS-LJ with low-jitter capability integrated into main board
    -- Versions supported: WRS-LJ v1.2
    --------------------------------------------------------------------------
    --------------------------------------------------------------------------
    -- Low-jitter daughterboard plugged onto a standard WRS
    -- (values "110" and "111" not used/allowed/set bythe LJ-Daugtherboard)
    --------------------------------------------------------------------------
    -- elsif (ljd_osc_freq_i != "111" ) then
    else
    dac_main_sync_n_o <= '0';
    dac_main_sclk_o <= '0';
    dac_main_data_o <= '0';
    lj_dac_main_sync_n_o <= dac_main_sync_n;
    lj_dac_main_sclk_o <= dac_main_sclk;
    lj_dac_main_data_o <= dac_main_data;
    lj_ext_gm_pll_pres_o <= '1';
    lj_ext_gm_clk_diff_o <= '1';
    end if;
    end process;
    -------------------------------------------------------------------------------
    lj_present <= '1' when ((lj_detected='1') and (lj_osc_freq_i/="111")) else '0';
    lj_detected_o <= lj_detected;
    lj_present_o <= lj_present;
    -- Redirect DAC output if external board detetected
    dac_redirection : process (lj_present, dac_main_sync_n, dac_main_sclk, dac_main_data)
    dac_redirection : process (lj_ext_gm_pll_pres, dac_main_sync_n, dac_main_sclk, dac_main_data)
    begin
    if (lj_present = '0') then
    dac_main_sync_n_o <= dac_main_sync_n;
    ......@@ -1357,6 +1430,5 @@ begin
    lj_dac_main_data_o <= dac_main_data;
    end if;
    end process;
    --
    end rtl;
    top/scb_18ports/scb_top_synthesis.ucf
    View file @ af344aa3
    ......@@ -25,9 +25,12 @@ INST "BUFGMUX_inst" LOC = BUFGCTRL_X0Y1;
    NET "lj_clk_62mhz_p_i" LOC = AN33;
    NET "lj_clk_62mhz_n_i" LOC = AN34;
    NET "lj_rev_id_i[0]" LOC = AE29;
    NET "lj_rev_id_i[1]" LOC = AE28;
    NET "lj_rev_id_i[2]" LOC = AM32;
    NET "lj_periph_id_i[0]" LOC = AE29;
    NET "lj_periph_id_i[0]" PULLUP;
    NET "lj_periph_id_i[1]" LOC = AE28;
    NET "lj_periph_id_i[1]" PULLUP;
    NET "lj_periph_id_i[2]" LOC = AM32;
    NET "lj_periph_id_i[2]" PULLUP;
    NET "lj_osc_freq_i[0]" LOC = AN32;
    NET "lj_osc_freq_i[0]" PULLUP;
    ......@@ -43,6 +46,10 @@ NET "lj_loopback_i" LOC = AM31;
    NET "lj_loopback_o" LOC = AL30;
    NET "lj_pll_locked_i" LOC = AH33;
    NET "wd_int_i" LOC = AC23;
    NET "wd_scl_i" LOC = T24;
    NET "wd_sda_b" LOC = T23;
    #EBI BUS
    #NET "cpu_clk_i" LOC="";
    NET "cpu_cs_n_i" LOC="H34";
    ......
    top/scb_18ports/scb_top_synthesis.vhd
    View file @ af344aa3
    ......@@ -157,7 +157,7 @@ entity scb_top_synthesis is
    lj_clk1_en : out std_logic;
    lj_clk2_en : out std_logic;
    lj_osc_freq_i : in std_logic_vector (2 downto 0);
    lj_rev_id_i : in std_logic_vector (2 downto 0);
    lj_periph_id_i: in std_logic_vector (2 downto 0);
    -------------------------------------------------------------------------------
    ......@@ -330,8 +330,18 @@ architecture Behavioral of scb_top_synthesis is
    signal clk_ext_100 : std_logic;
    signal ext_pll_100_locked, ext_pll_62_locked : std_logic;
    signal clk_ext_mul_locked : std_logic;
    signal lj_detected : std_logic := '0';
    signal lj_present : std_logic := '0';
    -- when lj_ext_gm_pll_pres = '0':
    -- FPGA-internal PLL is used to multiply input clock from 10MHz to 62.5MHz
    -- when lj_ext_gm_pll_pres = '1':
    -- external PLL is present and used to multiply input clock from 10MHz to 62.5MHz
    signal lj_ext_gm_pll_pres : std_logic := '0';
    -- when lj_ext_gm_clk_diff = '0'
    -- single-ended 10 MHz input clock at pin K13 is used as input for 10MHz signal to SoftPLL
    -- when lj_ext_gm_clk_diff = '1'
    -- differencial 10 MHz input clock at pin AF30/AG30 is used as input for 10MHz signal to SoftPLL
    signal lj_ext_gm_clk_diff : std_logic := '0';
    signal ext_clk_10MHz, ext_clk_10MHz_bufr, clk_10mhz : std_logic;
    signal lj_clk_62mhz, lj_clk_62mhz_bufr : std_logic;
    ......@@ -380,9 +390,10 @@ architecture Behavioral of scb_top_synthesis is
    lj_loopback_o : out std_logic;
    lj_clk1_en : out std_logic;
    lj_clk2_en : out std_logic;
    lj_detected_o : out std_logic;
    lj_present_o : out std_logic;
    lj_ext_gm_pll_pres_o : out std_logic;
    lj_ext_gm_clk_diff_o : out std_logic;
    lj_osc_freq_i : in std_logic_vector (2 downto 0);
    lj_periph_id_i : in std_logic_vector (2 downto 0);
    lj_pll_mosi_o : out std_logic;
    lj_pll_miso_i : in std_logic;
    lj_pll_sck_o : out std_logic;
    ......@@ -390,6 +401,9 @@ architecture Behavioral of scb_top_synthesis is
    lj_pll_sync_n_o : out std_logic;
    lj_pll_reset_n_o : out std_logic;
    lj_pll_locked_i : in std_logic;
    wd_int_i : in std_logic;
    wd_scl_i : in std_logic;
    wd_sda_b : inout std_logic;
    pll_status_i : in std_logic;
    pll_mosi_o : out std_logic;
    pll_miso_i : in std_logic;
    ......@@ -625,10 +639,10 @@ begin
    CE0 => '1',
    CE1 => '1',
    O => clk_10mhz,
    I0 => clk_ext,
    I1 => ext_clk_10MHz_bufr,
    S1 => lj_present,
    S0 => NOT lj_present);
    I0 => clk_ext, -- single-ended
    I1 => ext_clk_10MHz_bufr, -- differencial
    S1 => lj_ext_gm_clk_diff,
    S0 => NOT lj_ext_gm_clk_diff);
    U_Buf_CLK_DMTD : IBUFGDS
    generic map (
    ......@@ -684,7 +698,7 @@ begin
    clk_ext_i => clk_ext,
    clk_ext_100_o => clk_ext_100,
    rst_a_i => ext_pll_reset,
    powerdown_i => lj_detected,
    powerdown_i => lj_ext_gm_pll_pres,
    locked_o => ext_pll_100_locked);
    U_Ext_PLL2: ext_pll_100_to_62m
    ......@@ -692,7 +706,7 @@ begin
    clk_ext_100_i => clk_ext_100,
    clk_ext_mul_o => clk_ext_mul,
    rst_a_i => ext_pll_reset,
    powerdown_i => lj_detected,
    powerdown_i => lj_ext_gm_pll_pres,
    locked_o => ext_pll_62_locked);
    clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
    ......@@ -897,9 +911,10 @@ begin
    lj_loopback_o => lj_loopback_o,
    lj_clk1_en => lj_clk1_en,
    lj_clk2_en => lj_clk2_en,
    lj_detected_o => lj_detected,
    lj_present_o => lj_present,
    lj_ext_gm_pll_pres_o => lj_ext_gm_pll_pres,
    lj_ext_gm_clk_diff_o => lj_ext_gm_clk_diff,
    lj_osc_freq_i => lj_osc_freq_i,
    lj_periph_id_i => lj_periph_id_i,
    lj_pll_mosi_o => lj_pll_mosi_o,
    lj_pll_miso_i => lj_pll_miso_i,
    lj_pll_sck_o => lj_pll_sck_o,
    ......@@ -907,6 +922,10 @@ begin
    lj_pll_sync_n_o => lj_pll_sync_n_o,
    lj_pll_reset_n_o => lj_pll_reset_n_o,
    lj_pll_locked_i => lj_pll_locked_i,
    wd_int_i => wd_int_i,
    wd_scl_i => wd_scl_i,
    wd_sda_b => wd_sda_b,
    pll_status_i => clk_10mhz,
    pll_mosi_o => pll_mosi_o,
    ......
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