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White Rabbit Switch - Gateware
Commit aef7d8ab authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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update simulation manifests to use new hdlmake

parent 388f812d
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Showing with 83 additions and 20 deletions
testbench/10mhz_out/Manifest.py 0 → 100644
View file @ aef7d8ab
target = "xilinx"
action = "simulation"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX130T"
fetchto = "../../ip_cores"
#vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
files = [ "main.sv" ]
include_dirs = [ "../../sim", "../../sim/wr-hdl"]
modules = { "local" : ["../../top/bare_top",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"] }
testbench/nic_bw_throttling/Manifest.py
View file @ aef7d8ab
target = "xilinx"
action = "simulation"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX130T"
fetchto = "../../ip_cores"
vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
files = [ "main.sv" ]
include_dirs = [ "../../sim", "../../sim/wr-hdl"]
modules = { "local" : ["../../top/bare_top",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"] }
......
testbench/scb_network_top/Manifest.py
View file @ aef7d8ab
target = "xilinx"
action = "simulation"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX130T"
fetchto = "../../ip_cores"
vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
#vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
files = [ "main.sv" ]
include_dirs = [ "../../sim", "../../sim/wr-hdl" ]
modules = { "local" : ["../../", "../../top/bare_top"] }
......
testbench/scb_top/Manifest.py
View file @ aef7d8ab
target = "xilinx"
action = "simulation"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX130T"
fetchto = "../../ip_cores"
vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
#vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
files = [ "main.sv" ]
modules = { "local" : ["../../top/bare_top",
include_dirs = [ "../../sim", "../../sim/wr-hdl"]
modules = { "local" : [ "../../top/bare_top",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"] }
......
testbench/scb_top_8p/Manifest.py
View file @ aef7d8ab
target = "xilinx"
action = "simulation"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX130T"
fetchto = "../../ip_cores"
vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
#vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
files = [ "main.sv" ]
include_dirs = [ "../../sim", "../../sim/wr-hdl" ]
modules = { "local" : ["../../top/bare_top",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"] }
......
testbench/swc_async/mem/Manifest.py
View file @ aef7d8ab
action = "simulation"
target = "xilinx"
action = "simulation"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX240T"
fetchto = "../../../ip_cores"
vlog_opt = "+incdir+../../../sim +incdir+../../../ip_cores/general-cores/sim +incdir+../../../ip_cores/wr-cores/sim"
#vlog_opt = "+incdir+../../../sim +incdir+../../../ip_cores/general-cores/sim +incdir+../../../ip_cores/wr-cores/sim"
files = [ "main.sv" ]
include_dirs = [ "../../../sim", "../../../sim/wr-hdl" ]
modules = { "local" : [ "../../../modules/wrsw_swcore/mpm" ],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master"
}
......
testbench/swcore/Manifest.py
View file @ aef7d8ab
target = "xilinx" # "altera" #
action = "simulation"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX240T"
#fetchto = "../../ip_cores"
......@@ -13,16 +16,14 @@ files = [
"swc_core_generic.sv"
]
vlog_opt="+incdir+../../ip_cores/wr-cores/sim +incdir+../../ip_cores/wr-cores/sim/fabric_emu"
#vlog_opt="+incdir+../../ip_cores/wr-cores/sim +incdir+../../ip_cores/wr-cores/sim/fabric_emu"
include_dirs = [ "../../sim", "../../sim/wr-hdl" ]
modules = {"local":
[
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/ip_cores/general-cores/modules/genrams/",
"../../ip_cores/general-cores",
"../../modules/wrsw_swcore",
],
#"git" :
#[
#"git://ohwr.org/hdl-core-lib/general-cores.git",
#],
}
testbench/tru/Manifest.py
View file @ aef7d8ab
target = "xilinx" # "altera" #
action = "simulation"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX240T"
files = [
"tru.sv"
]
files = [ "tru.sv" ]
vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
include_dirs = [ "../../sim", "../../sim/wr-hdl" ]
modules = {"local":
[
"../../modules/wrsw_tru",
"../../ip_cores/wr-cores/ip_cores/general-cores/modules/genrams/"
"../../ip_cores/general-cores/modules/genrams/"
],
}
\ No newline at end of file
}
testbench/wrsw_pstats/Manifest.py
View file @ aef7d8ab
target = "xilinx"
action = "simulation"
syn_device = "XC6VLX130T"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX240T"
fetchto = "../../ip_cores"
vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
include_dirs = [ "../../sim", "../../sim/wr-hdl" ]
files = [ "main.sv" ]
modules ={"local" : ["../../ip_cores/general-cores",
......
testbench/wrsw_rt_subsystem/Manifest.py 0 → 100644
View file @ aef7d8ab
target = "xilinx"
action = "simulation"
sim_tool = "modelsim"
top_module = "main"
syn_device = "XC6VLX130T"
fetchto = "../../ip_cores"
vlog_opt = "+incdir+../../sim +incdir+../../sim/wr-hdl"
files = [ "main.sv" ]
include_dirs = [ "../../sim", "../../sim/wr-hdl" ]
modules = { "local" : ["../../top/bare_top",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"] }
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