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White Rabbit Switch - Gateware
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White Rabbit Switch - Gateware
Commits
ae063030
Commit
ae063030
authored
Dec 01, 2023
by
Maciej Lipinski
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CI: experiment
parent
d6d6b4e5
Pipeline
#5020
passed with stages
in 214 minutes and 50 seconds
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3
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57 additions
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-50
.gitlab-ci.yml
.gitlab-ci.yml
+52
-50
Manifest.py
syn/scb_18ports/Manifest.py
+2
-0
Manifest.py
syn/scb_8ports/Manifest.py
+3
-0
No files found.
.gitlab-ci.yml
View file @
ae063030
...
@@ -2,61 +2,63 @@ variables:
...
@@ -2,61 +2,63 @@ variables:
GIT_SUBMODULE_STRATEGY
:
normal
GIT_SUBMODULE_STRATEGY
:
normal
stages
:
stages
:
#
- sim
-
sim
-
syn
-
syn
#job_scb_top_sim:
job_scb_top_sim
:
# stage: sim
stage
:
sim
# tags:
when
:
manual
# - modelsim_10.2a
tags
:
# script:
-
modelsim_10.2a
# - /entrypoint.sh
script
:
# - source ~/setup_modelsim.sh
-
/entrypoint.sh
# - git submodule sync & git submodule update --init
-
source ~/setup_modelsim.sh
# - apt-get install -y python
-
git submodule sync & git submodule update --init
# - cd top/bare_top
-
apt-get install -y python
# - python gen_sdbsyn.py --project wr_switch
-
cd top/bare_top
# - cd ../../modules/wrsw_hwiu
-
python gen_sdbsyn.py --project wr_switch
# - python gen_ver.py
-
cd ../../modules/wrsw_hwiu
# - cd ../../
-
python gen_ver.py
# - cd sim
-
cd ../../
# - ln -s ../ip_cores/wr-cores/sim wr-hdl
-
cd sim
# - cd ../testbench/scb_top
-
ln -s ../ip_cores/wr-cores/sim wr-hdl
# - cp /opt/compiled_libs_ise14.7/modelsim.ini .
-
cd ../testbench/scb_top
# - hdlmake makefile
-
cp /opt/compiled_libs_ise14.7/modelsim.ini .
# - make
-
hdlmake makefile
# - vsim -c -do run.do
-
make
-
vsim -c -do run.do
#
job_scb_top_8p_syn:
job_scb_top_8p_syn
:
#
stage: syn
stage
:
syn
#
tags:
tags
:
#
- xilinx_ISE_14.7
-
xilinx_ISE_14.7
#
script:
script
:
#
- /entrypoint.sh
-
/entrypoint.sh
#
- source ~/setup_ise147.sh
-
source ~/setup_ise147.sh
#
- source /opt/Xilinx/14.7/ISE_DS/settings64.sh
-
source /opt/Xilinx/14.7/ISE_DS/settings64.sh
#
- cd top/bare_top
-
cd top/bare_top
#
- python gen_sdbsyn.py --project wr_switch
-
python gen_sdbsyn.py --project wr_switch
#
- cat synthesis_descriptor.vhd
-
cat synthesis_descriptor.vhd
#
- cd ../../modules/wrsw_hwiu
-
cd ../../modules/wrsw_hwiu
#
- python gen_ver.py
-
python gen_ver.py
#
- cat gw_ver_pkg.vhd
-
cat gw_ver_pkg.vhd
#
- cd ../../syn/scb_8ports
-
cd ../../syn/scb_8ports
#
- hdlmake makefile
-
hdlmake makefile
#
- make
-
make
#- bitgen
-intstyle ise -f scb_top_synthesis.ut scb_top_synthesis.ncd
-
bitgen -b
-intstyle ise -f scb_top_synthesis.ut scb_top_synthesis.ncd
#
artifacts:
artifacts
:
#
name: SCB_TOP_8P_CI_$CI_JOB_ID
name
:
SCB_TOP_8P_CI_$CI_JOB_ID
#
paths:
paths
:
#
- syn/scb_8ports/*.syr
-
syn/scb_8ports/*.syr
#
- syn/scb_8ports/*.mrp
-
syn/scb_8ports/*.mrp
#
- syn/scb_8ports/*.bit
-
syn/scb_8ports/*.bit
#
- syn/scb_8ports/*.bin
-
syn/scb_8ports/*.bin
#
- syn/scb_8ports/*.par
-
syn/scb_8ports/*.par
#
- syn/scb_8ports/*.twr
-
syn/scb_8ports/*.twr
job_scb_top_18p_syn
:
job_scb_top_18p_syn
:
stage
:
syn
stage
:
syn
when
:
manual
tags
:
tags
:
-
xilinx_ISE_14.7
-
xilinx_ISE_14.7
# only:
# only:
...
@@ -77,7 +79,7 @@ job_scb_top_18p_syn:
...
@@ -77,7 +79,7 @@ job_scb_top_18p_syn:
-
cd ../../syn/scb_18ports
-
cd ../../syn/scb_18ports
-
hdlmake makefile
-
hdlmake makefile
-
make
-
make
-
bitgen -intstyle ise -f scb_top_synthesis.ut scb_top_synthesis.ncd
-
bitgen -
b -
intstyle ise -f scb_top_synthesis.ut scb_top_synthesis.ncd
artifacts
:
artifacts
:
name
:
SCB_TOP_8P_CI_$CI_JOB_ID
name
:
SCB_TOP_8P_CI_$CI_JOB_ID
paths
:
paths
:
...
...
syn/scb_18ports/Manifest.py
View file @
ae063030
...
@@ -10,6 +10,8 @@ syn_grade = "-1"
...
@@ -10,6 +10,8 @@ syn_grade = "-1"
syn_package
=
"ff1156"
syn_package
=
"ff1156"
syn_top
=
"scb_top_synthesis"
syn_top
=
"scb_top_synthesis"
syn_project
=
"test_scb.xise"
syn_project
=
"test_scb.xise"
syn_pre_project_cmd
=
"python ../../modules/wrsw_hwiu/gen_ver.py"
syn_post_bitstream_cmd
=
"bitgen -intstyle ise -f scb_top_synthesis.ut -g Binary:yes scb_top_synthesis.ncd"
modules
=
{
"local"
:
[
"../../top/scb_18ports"
,
modules
=
{
"local"
:
[
"../../top/scb_18ports"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/general-cores"
,
...
...
syn/scb_8ports/Manifest.py
View file @
ae063030
...
@@ -10,7 +10,10 @@ syn_grade = "-1"
...
@@ -10,7 +10,10 @@ syn_grade = "-1"
syn_package
=
"ff1156"
syn_package
=
"ff1156"
syn_top
=
"scb_top_synthesis"
syn_top
=
"scb_top_synthesis"
syn_project
=
"test_scb.xise"
syn_project
=
"test_scb.xise"
syn_pre_project_cmd
=
"python ../../modules/wrsw_hwiu/gen_ver.py"
syn_post_bitstream_cmd
=
"bitgen -intstyle ise -f scb_top_synthesis.ut -g Binary:yes scb_top_synthesis.ncd"
modules
=
{
"local"
:
[
"../../top/scb_8ports"
,
modules
=
{
"local"
:
[
"../../top/scb_8ports"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/wr-cores"
]
}
"../../ip_cores/wr-cores"
]
}
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