swcore: update

aaa7c3db · Maciej Lipinski · 8070fb92 · aaa7c3db · aaa7c3db · aaa7c3db
Commit aaa7c3db authored Dec 01, 2010 by Maciej Lipinski
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Showing with 34 additions and 92 deletions

fabric_emu.sv fabric_emu.sv +4 -2

sim_input_block.do sim_input_block.do +1 -82

swc_core.v4.sv swc_core.v4.sv +29 -8

vsim.wlf vsim.wlf +0 -0

No files found.
--- a/fabric_emu.sv
+++ b/fabric_emu.sv
@@ -424,7 +424,7 @@ module fabric_emu
      
      wait_clk();

-      while(!tx_eof_p1_i && !tx_rerror_p1_i) begin
+      while(1) begin //while(!tx_eof_p1_i && !tx_rerror_p1_i) begin

 	 // simulate the flow throttling	 
 	 if(SIM.sim_rx_throttle && probability_hit(SIM.rx_throttle_prob, 100))
@@ -451,6 +451,8 @@ module fabric_emu
 	    i++;
 	 end
      
+      if(tx_eof_p1_i || tx_rerror_p1_i) break;
+      
 	 wait_clk();
      end

@@ -500,7 +502,7 @@ module fabric_emu
      frame.size 	      = payload_len;
      frame.error 	      = error;

-//      dump_frame_header("RX: ", frame);
+     // dump_frame_header("RX: ", frame);
      rx_queue.push(frame);
      
      

--- a/sim_input_block.do
+++ b/sim_input_block.do
@@ -11,88 +11,7 @@ radix -hexadecimal

 do wave.do

-add wave \
-{sim:/main/clk } \
-{sim:/main/a_to_input_block_data } \
-{sim:/main/a_to_input_block_ctrl } \
-{sim:/main/a_to_input_block_bytesel } \
-{sim:/main/a_to_input_block_dreq } \
-{sim:/main/a_to_input_block_valid } \
-{sim:/main/a_to_input_block_sof_p1 } \
-{sim:/main/a_to_input_block_eof_p1 } \
-{sim:/main/a_to_input_block_rerror_p1 } \
-{sim:/main/mmu_page_alloc_req } \
-{sim:/main/mmu_page_alloc_done } \
-{sim:/main/mmu_pageaddr_in } \
-{sim:/main/mmu_pageaddr_out } \
-{sim:/main/mmu_force_free } \
-{sim:/main/mmu_set_usecnt } \
-{sim:/main/mmu_set_usecnt_done } \
-{sim:/main/mmu_usecnt } \
-{sim:/main/rtu_rsp_valid } \
-{sim:/main/rtu_rsp_ack } \
-{sim:/main/rtu_dst_port_mask } \
-{sim:/main/rtu_drop } \
-{sim:/main/rtu_prio } \
-{sim:/main/mpm_pckstart } \
-{sim:/main/mpm_pageaddr } \
-{sim:/main/mpm_pageend } \
-{sim:/main/mpm_data } \
-{sim:/main/mpm_drdy } \
-{sim:/main/mpm_full } \
-{sim:/main/mpm_flush } \
-{sim:/main/pta_transfer_pck } \
-{sim:/main/pta_pageaddr } \
-{sim:/main/pta_mask } \
-{sim:/main/pta_prio } \
-{sim:/main/rst } 
-add wave \
-{sim:/main/DUT/clk_i } \
-{sim:/main/DUT/rst_n_i } \
-{sim:/main/DUT/tx_sof_p1_i } \
-{sim:/main/DUT/tx_eof_p1_i } \
-{sim:/main/DUT/tx_data_i } \
-{sim:/main/DUT/tx_ctrl_i } \
-{sim:/main/DUT/tx_valid_i } \
-{sim:/main/DUT/tx_bytesel_i } \
-{sim:/main/DUT/tx_dreq_o } \
-{sim:/main/DUT/tx_abort_p1_i } \
-{sim:/main/DUT/tx_rerror_p1_i } \
-{sim:/main/DUT/mmu_page_alloc_req_o } \
-{sim:/main/DUT/mmu_page_alloc_done_i } \
-{sim:/main/DUT/mmu_pageaddr_i } \
-{sim:/main/DUT/mmu_pageaddr_o } \
-{sim:/main/DUT/mmu_force_free_o } \
-{sim:/main/DUT/mmu_set_usecnt_o } \
-{sim:/main/DUT/mmu_set_usecnt_done_i } \
-{sim:/main/DUT/mmu_usecnt_o } \
-{sim:/main/DUT/rtu_rsp_valid_i } \
-{sim:/main/DUT/rtu_rsp_ack_o } \
-{sim:/main/DUT/rtu_dst_port_mask_i } \
-{sim:/main/DUT/rtu_drop_i } \
-{sim:/main/DUT/rtu_prio_i } \
-{sim:/main/DUT/mpm_pckstart_o } \
-{sim:/main/DUT/mpm_pageaddr_o } \
-{sim:/main/DUT/mpm_pagereq_o } \
-{sim:/main/DUT/mpm_pageend_i } \
-{sim:/main/DUT/mpm_data_o } \
-{sim:/main/DUT/mpm_drdy_o } \
-{sim:/main/DUT/mpm_full_i } \
-{sim:/main/DUT/mpm_flush_o } \
-{sim:/main/DUT/pta_transfer_pck_o } \
-{sim:/main/DUT/pta_pageaddr_o } \
-{sim:/main/DUT/pta_mask_o } \
-{sim:/main/DUT/pta_prio_o } \
-{sim:/main/DUT/page_in_advance_allocated } \
-{sim:/main/DUT/mmu_page_alloc_req } \
-{sim:/main/DUT/rtu_rsp_valid_d1 } \
-{sim:/main/DUT/tx_dreq } \
-{sim:/main/DUT/rtu_drop } \
-{sim:/main/DUT/usecnt } \
-{sim:/main/DUT/set_usecnt } \
-{sim:/main/DUT/mpm_pckstart } \
-{sim:/main/DUT/mpm_pagereq } \
-{sim:/main/DUT/mpm_flush } 
+

 run 3us
 wave zoomfull

--- a/swc_core.v4.sv
+++ b/swc_core.v4.sv
@@ -380,16 +380,18 @@ module main;
        $display("Initial waiting: %d cycles",((port*50)%11)*50);
        wait_cycles(((port*50)%11)*50);
        
-        for(i=25;i<1250;i=i+25)
+        for(i=400;i<1250;i=i+25)
        begin
          hdr.src          = port << 44 | cnt ;
          hdr.port_id      = port;
          hdr.ethertype    = i;

  //        mask = 'h00F;;          
-  //      mask = 'h7FF;;
+   //       mask = 'h7FF;;
          mask = (4*cnt + 3*cnt + 2*cnt + cnt)%2047; 
          if( (i/50)%20 > 10) drop = 1; else drop = 0;
+     //     drop = 0;
+          
          
          send_pck(hdr,buffer, i, port, drop,  (i/50)%7, mask, cnt);  
          
@@ -433,11 +435,30 @@ module main;
      wait(test_input_block_9.ready);
      wait(test_input_block_10.ready);
      
-     // test_input_block_1.simulate_tx_throttling(1, 10);
-      
-      //      test_input_block_0.simulate_rx_abort(1,80);
-            test_input_block_1.simulate_tx_error(1,100);
-      //      test_input_block_1.send(hdr, buffer, 911);
+  
+     test_input_block_0.simulate_tx_throttling(1, 10);
+     test_input_block_1.simulate_tx_throttling(1, 20);
+     test_input_block_2.simulate_tx_throttling(1, 30);
+     test_input_block_3.simulate_tx_throttling(1, 40);
+     test_input_block_4.simulate_tx_throttling(1, 10);
+     test_input_block_5.simulate_tx_throttling(1, 20);
+     test_input_block_6.simulate_tx_throttling(1, 30);
+     test_input_block_7.simulate_tx_throttling(1, 40);
+     test_input_block_8.simulate_tx_throttling(1, 10);
+     test_input_block_9.simulate_tx_throttling(1, 20);
+     test_input_block_10.simulate_tx_throttling(1,40);
+
+
+
+     test_input_block_0.simulate_rx_throttling(1, 10);
+     test_input_block_1.simulate_rx_throttling(1, 20);
+     test_input_block_2.simulate_rx_throttling(1, 10);
+     test_input_block_3.simulate_rx_throttling(1, 20);
+
+
+     //test_input_block_0.simulate_tx_error(1,110);
+     //      test_input_block_0.simulate_rx_abort(1,80);
+     //      test_input_block_1.send(hdr, buffer, 911);
      
      
      ports_read = 1;
@@ -505,7 +526,7 @@ module main;
   end
   initial begin
      wait(ports_read);
-      load_port(10);
+     load_port(10);
      tx_port_finished[10] = 1;
   end  
           

--- a/vsim.wlf
+++ b/vsim.wlf