Commit a3071cad authored by Konstantinos Blantos's avatar Konstantinos Blantos

Update .gitlab-ci.yml

parent 24bbf09b
......@@ -29,7 +29,7 @@ job_scb_top_8p_sim:
- apt-get install -y python
- cd top/bare_top
- python gen_sdbsyn.py
- cat synthesis_descriptor.vhd
- cat synthesis_descriptor.vhd --project wr_switch
- cd ../../
- cd sim
- ln -s ../ip_cores/wr-cores/sim wr-hdl
......
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