added chipscipe to tx/rx prots

9dbb5aea · Maciej Lipinski · 1d500455 · 9dbb5aea
Commit 9dbb5aea authored Jan 11, 2021 by Maciej Lipinski
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Showing with 80 additions and 33 deletions

scb_top_bare.vhd top/bare_top/scb_top_bare.vhd +80 -33

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--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -318,7 +318,8 @@ architecture rtl of scb_top_bare is
  type t_trig is array(integer range <>) of std_logic_vector(31 downto 0);

  signal control0                   : std_logic_vector(35 downto 0);
-  signal trig0, trig1, trig2, trig3 : t_trig(7 downto 0);--std_logic_vector(31 downto 0);
+--   signal trig0, trig1, trig2, trig3 : t_trig(7 downto 0);--std_logic_vector(31 downto 0);
+  signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
  signal t0, t1, t2, t3             : std_logic_vector(31 downto 0);
  signal rst_n_periph               : std_logic;
  signal link_kill                  : std_logic_vector(c_NUM_PORTS-1 downto 0);
@@ -430,20 +431,66 @@ begin



-  --CS_ICON : chipscope_icon
-  --  port map (
-  --   CONTROL0 => CONTROL0);
-  --CS_ILA : chipscope_ila
-  --  port map (
-  --    CONTROL => CONTROL0,
-
-  --    CLK     => clk_sys,
-  --    TRIG0   => TRIG0,
-  --    TRIG1   => TRIG1,
-  --    TRIG2   => TRIG2,
-  --    TRIG3   => TRIG3);
-
-
+  CS_ICON : chipscope_icon
+   port map (
+    CONTROL0 => CONTROL0);
+  CS_ILA : chipscope_ila
+   port map (
+     CONTROL => CONTROL0,
+
+     CLK     => clk_sys,
+     TRIG0   => TRIG0,
+     TRIG1   => TRIG1,
+     TRIG2   => TRIG2,
+     TRIG3   => TRIG3);
+
+  -- rx wrong data
+  TRIG0( 15 downto  0)  <= endpoint_snk_in(2).dat;
+  TRIG0( 17 downto 16)  <= endpoint_snk_in(2).adr;
+  TRIG0(           18)  <= endpoint_snk_in(2).cyc;
+  TRIG0(           19)  <= endpoint_snk_in(2).stb;
+  TRIG0(           20)  <= endpoint_snk_in(2).we;
+  TRIG0(           21)  <= std_logic(endpoint_snk_in(2).sel(0) xor endpoint_snk_in(2).sel(1));
+  TRIG0(           22)  <= endpoint_snk_out(2).ack;
+  TRIG0(           23)  <= endpoint_snk_out(2).stall;
+  TRIG0(           24)  <= endpoint_snk_out(2).err;
+  TRIG0(           25)  <= endpoint_snk_out(2).rty;
+  TRIG0(           26)  <= phys_i(2).tx_disparity;
+  TRIG0(           27)  <= phys_i(2).rx_enc_err;
+  TRIG0( 29 downto 28)  <= phys_i(2).rx_k;
+  TRIG0( 31 downto 30)  <= phys_i(2).rx_data(15 downto 14);
+
+  -- tx wrong data (hanging)
+  TRIG1( 15 downto  0)  <= endpoint_src_out(3).dat;
+  TRIG1( 17 downto 16)  <= endpoint_src_out(3).adr;
+  TRIG1(           18)  <= endpoint_src_out(3).cyc;
+  TRIG1(           19)  <= endpoint_src_out(3).stb;
+  TRIG1(           20)  <= endpoint_src_out(3).we;
+  TRIG1(           21)  <= std_logic(endpoint_snk_in(3).sel(0) xor endpoint_snk_in(3).sel(1));
+  TRIG1(           22)  <= endpoint_src_in(3).ack;
+  TRIG1(           23)  <= endpoint_src_in(3).stall;
+  TRIG1(           24)  <= endpoint_src_in(3).err;
+  TRIG1(           25)  <= endpoint_src_in(3).rty;
+  TRIG1( 31 downto 26)  <= phys_i(2).rx_data(5 downto 0);
+
+  TRIG2(  3 downto  0) <= swc_wdog_out(2)(c_ALLOC_FSM_IDX);
+  TRIG2(  7 downto  4) <= swc_wdog_out(2)(c_TRANS_FSM_IDX);
+  TRIG2( 11 downto  8) <= swc_wdog_out(2)(c_RCV_FSM_IDX);
+  TRIG2( 15 downto 12) <= swc_wdog_out(2)(c_LL_FSM_IDX);
+  TRIG2( 19 downto 16) <= swc_wdog_out(2)(c_PREP_FSM_IDX);
+  TRIG2( 23 downto 20) <= swc_wdog_out(2)(c_SEND_FSM_IDX);
+  TRIG2( 27 downto 24) <= swc_wdog_out(2)(c_FREE_FSM_IDX);
+  TRIG2( 31 downto 28) <= phys_i(2).rx_data(9 downto 6);
+
+  TRIG3(  3 downto  0) <= swc_wdog_out(3)(c_ALLOC_FSM_IDX);
+  TRIG3(  7 downto  4) <= swc_wdog_out(3)(c_TRANS_FSM_IDX);
+  TRIG3( 11 downto  8) <= swc_wdog_out(3)(c_RCV_FSM_IDX);
+  TRIG3( 15 downto 12) <= swc_wdog_out(3)(c_LL_FSM_IDX);
+  TRIG3( 19 downto 16) <= swc_wdog_out(3)(c_PREP_FSM_IDX);
+  TRIG3( 23 downto 20) <= swc_wdog_out(3)(c_SEND_FSM_IDX);
+  TRIG3( 27 downto 24) <= swc_wdog_out(3)(c_FREE_FSM_IDX);
+  TRIG3( 31 downto 28) <= phys_i(2).rx_data(13 downto 10);
+  
  cnx_slave_in(0) <= cpu_wb_i;
  cpu_wb_o        <= cnx_slave_out(0);

@@ -1168,23 +1215,23 @@ begin
    swc_snk_in    <= wrfreg_src_out;
  end generate;

-  gen_muxed_CS: if g_with_muxed_CS = true generate
-    CS_ICON : chipscope_icon
-     port map (
-      CONTROL0 => CONTROL0);
-    CS_ILA : chipscope_ila
-     port map (
-       CONTROL => CONTROL0,
-       CLK     => clk_sys, --phys_i(0).rx_clk,
-       TRIG0   => T0,
-       TRIG1   => T1,
-       TRIG2   => T2,
-       TRIG3   => T3);
-  
-       T0   <= TRIG0(to_integer(unsigned(dbg_chps_id)));
-       T1   <= TRIG1(to_integer(unsigned(dbg_chps_id)));
-       T2   <= TRIG2(to_integer(unsigned(dbg_chps_id)));
-       T3   <= TRIG3(to_integer(unsigned(dbg_chps_id)));
-  end generate;
+--   gen_muxed_CS: if g_with_muxed_CS = true generate
+--     CS_ICON : chipscope_icon
+--      port map (
+--       CONTROL0 => CONTROL0);
+--     CS_ILA : chipscope_ila
+--      port map (
+--        CONTROL => CONTROL0,
+--        CLK     => clk_sys, --phys_i(0).rx_clk,
+--        TRIG0   => T0,
+--        TRIG1   => T1,
+--        TRIG2   => T2,
+--        TRIG3   => T3);
+--   
+--        T0   <= TRIG0(to_integer(unsigned(dbg_chps_id)));
+--        T1   <= TRIG1(to_integer(unsigned(dbg_chps_id)));
+--        T2   <= TRIG2(to_integer(unsigned(dbg_chps_id)));
+--        T3   <= TRIG3(to_integer(unsigned(dbg_chps_id)));
+--   end generate;
  
 end rtl;