Skip to content

W
White Rabbit Switch - Gateware
Commit 9986355b authored by Maciej Lipinski's avatar Maciej Lipinski
Browse files
Options

swcore[v2->v3 port] wrappers for the wishbonized (xswc_core) swcore written,… 

swcore[v2->v3 port] wrappers for the wishbonized (xswc_core) swcore written, they enable the pWB emulators to talk to xswc_core (two wrappers needed). added simulation (xswc_core.sv) which instanciates 7 ports and wrapped xswc_core)
parent 043a60ca
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 867 additions and 5 deletions
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ 9986355b
......@@ -54,7 +54,7 @@ package swc_swcore_pkg is
-- number of switch ports
constant c_swc_num_ports : integer := 11;--7; --c_NUM_PORTS
constant c_swc_num_ports : integer := 7; --c_NUM_PORTS
-- size of the packet memory in words (1 word = 1 ctrl + data sequence)
constant c_swc_packet_mem_size : integer := 65536;
......
modules/wrsw_swcore/xswc_core.vhd
View file @ 9986355b
......@@ -226,7 +226,7 @@ begin
rst_n_i => rst_n_i,
snk_i => snk_i(i),
snk_o => snk_o(i),
addr_o => swc_snk_ctrl((i+1)*c_swc_ctrl_width - 1 downto i*c_swc_ctrl_width),
addr_o => swc_snk_ctrl((i+1)*c_swc_ctrl_width - 3 downto i*c_swc_ctrl_width),
data_o => swc_snk_data((i+1)*c_swc_data_width - 1 downto i*c_swc_data_width),
dvalid_o => swc_snk_valid(i),
sof_o => swc_snk_sof_p1(i),
......@@ -243,7 +243,7 @@ begin
rst_n_i => rst_n_i,
src_i => src_i(i),
src_o => src_o(i),
addr_i => swc_src_ctrl((i+1)*c_swc_ctrl_width - 1 downto i*c_swc_ctrl_width),
addr_i => swc_src_ctrl((i+1)*c_swc_ctrl_width - 3 downto i*c_swc_ctrl_width),
data_i => swc_src_data((i+1)*c_swc_data_width - 1 downto i*c_swc_data_width),
dvalid_i => swc_src_valid(i),
sof_i => swc_src_sof_p1(i),
......
testbench/swcore/Manifest.py
View file @ 9986355b
......@@ -3,9 +3,16 @@ action = "simulation"
#fetchto = "../../ip_cores"
files = "swc_core.v4.sv"
#files = "swc_core.v4.sv"
vlog_opt="+incdir+../../../sim "
files = [
"xswc_core_7_ports_wrapper.vhd",
"swcore_wrapper.svh",
"xswc_core.sv"
]
#vlog_opt="+incdir+../../../sim "
vlog_opt="+incdir+../../ip_cores/wr-cores/sim +incdir+../../ip_cores/wr-cores/sim/fabric_emu"
modules = {"local":
[
......
testbench/swcore/swcore_wrapper.svh 0 → 100644
View file @ 9986355b
`define PORT_NUMBER 7
`define PORT_PRIO_W 3
`define WIRE_WB_SINK(iface, nr, prefix) \
.prefix``_adr_``nr``_i(iface.adr), \
.prefix``_dat_``nr``_i(iface.dat_o), \
.prefix``_stb_``nr``_i(iface.stb), \
.prefix``_sel_``nr``_i(iface.sel), \
.prefix``_cyc_``nr``_i(iface.cyc), \
.prefix``_ack_``nr``_o(iface.ack), \
.prefix``_err_``nr``_o(iface.err), \
.prefix``_stall_``nr``_o(iface.stall)
`define WIRE_WB_SOURCE(iface, nr, prefix) \
.prefix``_adr_``nr``_o(iface.adr), \
.prefix``_dat_``nr``_o(iface.dat_i), \
.prefix``_stb_``nr``_o(iface.stb), \
.prefix``_sel_``nr``_o(iface.sel), \
.prefix``_cyc_``nr``_o(iface.cyc), \
.prefix``_ack_``nr``_i(iface.ack), \
.prefix``_err_``nr``_i(iface.err), \
.prefix``_stall_``nr``_i(iface.stall)
module swcore_wrapper
(
input clk_i,
input rst_n_i,
IWishboneMaster.master src_0,
IWishboneMaster.master src_1,
IWishboneMaster.master src_2,
IWishboneMaster.master src_3,
IWishboneMaster.master src_4,
IWishboneMaster.master src_5,
IWishboneMaster.master src_6,
IWishboneSlave.slave snk_0,
IWishboneSlave.slave snk_1,
IWishboneSlave.slave snk_2,
IWishboneSlave.slave snk_3,
IWishboneSlave.slave snk_4,
IWishboneSlave.slave snk_5,
IWishboneSlave.slave snk_6,
input [`PORT_NUMBER-1 :0] rtu_rsp_valid_i,
output [`PORT_NUMBER-1 :0] rtu_rsp_ack_o,
input [`PORT_NUMBER*`PORT_NUMBER-1 :0] rtu_dst_port_mask_i,
input [`PORT_NUMBER-1 :0] rtu_drop_i,
input [`PORT_NUMBER*`PORT_PRIO_W-1 :0] rtu_prio_i
);
xswc_core_7_ports_wrapper
#(
.g_swc_num_ports (`PORT_NUMBER),
.g_swc_prio_width(`PORT_PRIO_W)
) DUT (
.clk_i (clk_i),
.rst_n_i (rst_n_i),
`WIRE_WB_SINK(src_0, 0, snk),
`WIRE_WB_SINK(src_1, 1, snk),
`WIRE_WB_SINK(src_2, 2, snk),
`WIRE_WB_SINK(src_3, 3, snk),
`WIRE_WB_SINK(src_4, 4, snk),
`WIRE_WB_SINK(src_5, 5, snk),
`WIRE_WB_SINK(src_6, 6, snk),
`WIRE_WB_SOURCE(snk_0, 0, src),
`WIRE_WB_SOURCE(snk_1, 1, src),
`WIRE_WB_SOURCE(snk_2, 2, src),
`WIRE_WB_SOURCE(snk_3, 3, src),
`WIRE_WB_SOURCE(snk_4, 4, src),
`WIRE_WB_SOURCE(snk_5, 5, src),
`WIRE_WB_SOURCE(snk_6, 6, src),
.rtu_rsp_valid_i (rtu_rsp_valid_i),
.rtu_rsp_ack_o (rtu_rsp_ack_o),
.rtu_dst_port_mask_i (rtu_dst_port_mask_i),
.rtu_drop_i (rtu_drop_i),
.rtu_prio_i (rtu_prio_i)
);
endmodule // endpoint_phy_wrapper
testbench/swcore/xswc_core.sv 0 → 100644
View file @ 9986355b
// Fabric emulator example, showing 2 fabric emulators connected together and exchanging packets.
`define c_clock_period 8
`define c_swc_page_addr_width 10
`define c_swc_usecount_width 4
`define c_wrsw_prio_width 3
`define c_swc_ctrl_width 4
`define c_swc_data_width 16
`define c_wrsw_num_ports 11
//`define c_wrsw_num_ports 7
`timescale 1ns / 1ps
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
`include "wb_packet_source.svh"
`include "wb_packet_sink.svh"
`include "swcore_wrapper.svh"
`define array_copy(a, ah, al, b, bl) \
for (k=al; k<=ah; k=k+1) a[k] <= b[bl+k-al];
typedef struct {
int cnt;
int usecnt[10];
int port[10];
} alloc_info_t;
alloc_info_t alloc_table[1024];
alloc_info_t dealloc_table[1024];
int stack_bastard = 0;
int pg_alloc_cnt[1024][20];
int pg_dealloc_cnt[1024][20];
module main;
reg clk = 0;
reg rst_n = 0;
IWishboneMaster
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_source_0
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneMaster
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_source_1
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneMaster
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_source_2
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneMaster
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_source_3
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneMaster
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_source_4
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneMaster
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_source_5
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneMaster
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_source_6
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneSlave
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_sink_0
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneSlave
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_sink_1
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneSlave
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_sink_2
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneSlave
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_sink_3
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneSlave
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_sink_4
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneSlave
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_sink_5
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneSlave
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_sink_6
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
reg [`c_wrsw_num_ports-1:0] rtu_rsp_valid = 0;
wire [`c_wrsw_num_ports-1:0] rtu_rsp_ack;
reg [`c_wrsw_num_ports * `c_wrsw_num_ports - 1 : 0] rtu_dst_port_mask = 0;
reg [`c_wrsw_num_ports-1:0] rtu_drop = 0;
reg [`c_wrsw_num_ports * `c_wrsw_prio_width -1 : 0] rtu_prio = 0;
// generate clock and reset signals
always #(`c_clock_period/2) clk <= ~clk;
initial begin
repeat(3) @(posedge clk);
rst_n = 1;
end
int tx_cnt_0[11];
int tx_cnt_1[11];
int tx_cnt_2[11];
int tx_cnt_3[11];
int tx_cnt_4[11];
int tx_cnt_5[11];
int tx_cnt_6[11];
int tx_cnt_7[11];
int tx_cnt_8[11];
int tx_cnt_9[11];
int tx_cnt_10[11];
int rx_cnt[11];
int tx_cnt_by_port[11][11];
int rx_cnt_by_port[11][11];
int rx_cnt_0[11];
int rx_cnt_1[11];
int rx_cnt_2[11];
int rx_cnt_3[11];
int rx_cnt_4[11];
int rx_cnt_5[11];
int rx_cnt_6[11];
int rx_cnt_7[11];
int rx_cnt_8[11];
int rx_cnt_9[11];
int rx_cnt_10[11];
bit [10:0] tx_port_finished = 0;//{0,0,0,0,0,0,0,0,0,0,0};
integer ports_read = 0;
swcore_wrapper
DUT (
.clk_i (clk),
.rst_n_i (rst_n),
//-------------------------------------------------------------------------------
//-- Fabric I/F
//-------------------------------------------------------------------------------
.snk_0 (U_wrf_sink_0.slave),
.snk_1 (U_wrf_sink_1.slave),
.snk_2 (U_wrf_sink_2.slave),
.snk_3 (U_wrf_sink_3.slave),
.snk_4 (U_wrf_sink_4.slave),
.snk_5 (U_wrf_sink_5.slave),
.snk_6 (U_wrf_sink_6.slave),
//-------------------------------------------------------------------------------
//-- Fabric I/F : output (goes to the Endpoint)
//-------------------------------------------------------------------------------
.src_0(U_wrf_source_0.master),
.src_1(U_wrf_source_1.master),
.src_2(U_wrf_source_2.master),
.src_3(U_wrf_source_3.master),
.src_4(U_wrf_source_4.master),
.src_5(U_wrf_source_5.master),
.src_6(U_wrf_source_6.master),
//-------------------------------------------------------------------------------
//-- I/F with Routing Table Unit (RTU)
//-------------------------------------------------------------------------------
.rtu_rsp_valid_i (rtu_rsp_valid),
.rtu_rsp_ack_o (rtu_rsp_ack),
.rtu_dst_port_mask_i (rtu_dst_port_mask),
.rtu_drop_i (rtu_drop),
.rtu_prio_i (rtu_prio)
);
task automatic wait_cycles;
input [31:0] ncycles;
begin : wait_body
integer i;
for(i=0;i<ncycles;i=i+1) @(posedge clk);
end
endtask // wait_cycles
endmodule // main
testbench/swcore/xswc_core_7_ports_wrapper.vhd 0 → 100644
View file @ 9986355b
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment