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White Rabbit Switch - Gateware
Commit 9540c282 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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fall back to previous verions of SoftPLL HDL for v4.0 release

parent a9faef63
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Showing with 13 additions and 3 deletions
wr-cores @ 470567fe
Subproject commit 8838a6448bbe6c28b02afa19f79e24a2cf35512e
Subproject commit 470567fec7e14e6415fbdef0e38f7b3b008dce0c
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 9540c282
......@@ -117,10 +117,15 @@ architecture rtl of wrsw_rt_subsystem is
g_tag_bits : integer;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_with_period_detector : boolean;
g_with_debug_fifo : boolean;
g_with_ext_clock_input : boolean;
g_divide_input_by_2 : boolean;
g_with_undersampling : boolean;
g_divide_input_by_2 : boolean;
g_reverse_dmtds : boolean;
g_bb_ref_divider : integer;
g_bb_feedback_divider : integer;
g_bb_log2_gating : integer;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
......@@ -316,7 +321,12 @@ begin -- rtl
g_reverse_dmtds => true,
g_with_ext_clock_input => true,
g_divide_input_by_2 => false,
g_with_debug_fifo => true)
g_with_period_detector => false,
g_with_undersampling => false,
g_with_debug_fifo => true,
g_bb_ref_divider => 8,
g_bb_feedback_divider => 25,
g_bb_log2_gating => 13)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......
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