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White Rabbit Switch - Gateware
Commit 8cd88347 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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syn,top/scb_6ports_omb: removed obsolete top levels

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syn/scb_6ports_omb/Manifest.py deleted 100644 → 0
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target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
syn_device = "xc6vlx130t"
syn_grade = "-1"
syn_package = "ff1156"
syn_top = "scb_top_synthesis"
syn_project = "scb_6ports_omb.xise"
modules = { "local" : [ "../../top/scb_6ports_omb" ] }
syn/scb_6ports_omb/scb_6ports_omb.xise deleted 100644 → 0
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top/scb_6ports_omb/Manifest.py deleted 100644 → 0
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files = ["scb_top_synthesis.ucf", "scb_top_synthesis.vhd"];
modules = { "local" : [ "../../", "../bare_top" ] };
top/scb_6ports_omb/scb_top_synthesis.ucf deleted 100644 → 0
View file @ a7384a41
NET "sys_rst_n_i" LOC="M10";
# CLK
NET "fpga_clk_25mhz_p_i" LOC=K24;
NET "fpga_clk_25mhz_n_i" LOC=K23;
NET "fpga_clk_ref_p_i" LOC=J9;
NET "fpga_clk_ref_n_i" LOC=H9;
NET "fpga_clk_aux_p_i" LOC=A10;
NET "fpga_clk_aux_n_i" LOC=B10;
NET "fpga_clk_dmtd_p_i" LOC=L23;
NET "fpga_clk_dmtd_n_i" LOC=M22;
#EBI BUS
#NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34";
NET "cpu_wr_n_i" LOC="M25";
NET "cpu_rd_n_i" LOC="J31";
NET "cpu_bs_n_i<0>" LOC="J30";
NET "cpu_bs_n_i<1>" LOC="P29";
NET "cpu_bs_n_i<2>" LOC="H30";
NET "cpu_bs_n_i<3>" LOC="J34";
NET "cpu_nwait_o" LOC="R26";
NET "cpu_irq_n_o" LOC="AC24";
NET "cpu_addr_i<18>" LOC="M28";
NET "cpu_addr_i<17>" LOC="M30";
NET "cpu_addr_i<16>" LOC="C32";
NET "cpu_addr_i<15>" LOC="L31";
NET "cpu_addr_i<14>" LOC="L25";
NET "cpu_addr_i<13>" LOC="B33";
NET "cpu_addr_i<12>" LOC="B32";
NET "cpu_addr_i<11>" LOC="C33";
NET "cpu_addr_i<10>" LOC="L26";
NET "cpu_addr_i<9>" LOC="H32";
NET "cpu_addr_i<8>" LOC="G32";
NET "cpu_addr_i<7>" LOC="E32";
NET "cpu_addr_i<6>" LOC="F30";
NET "cpu_addr_i<5>" LOC="D31";
NET "cpu_addr_i<4>" LOC="L28";
NET "cpu_addr_i<3>" LOC="E33";
NET "cpu_addr_i<2>" LOC="J27";
NET "cpu_addr_i<1>" LOC="G31";
NET "cpu_addr_i<0>" LOC="D32";
#NET "cpu_addr_i<1>" LOC="H30";
#NET "cpu_addr_i<0>" LOC="J30";
NET "cpu_data_b<31>" LOC="T26";
NET "cpu_data_b<30>" LOC="R28";
NET "cpu_data_b<29>" LOC="R29";
NET "cpu_data_b<28>" LOC="N34";
NET "cpu_data_b<27>" LOC="P34";
NET "cpu_data_b<26>" LOC="P25";
NET "cpu_data_b<25>" LOC="L34";
NET "cpu_data_b<24>" LOC="R32";
NET "cpu_data_b<23>" LOC="R27";
NET "cpu_data_b<22>" LOC="P27";
NET "cpu_data_b<21>" LOC="P26";
NET "cpu_data_b<20>" LOC="K34";
NET "cpu_data_b<19>" LOC="M31";
NET "cpu_data_b<18>" LOC="R31";
NET "cpu_data_b<17>" LOC="N30";
NET "cpu_data_b<16>" LOC="N25";
NET "cpu_data_b<15>" LOC="L33";
NET "cpu_data_b<14>" LOC="K31";
NET "cpu_data_b<13>" LOC="K29";
NET "cpu_data_b<12>" LOC="K33";
NET "cpu_data_b<11>" LOC="J29";
NET "cpu_data_b<10>" LOC="K32";
NET "cpu_data_b<9>" LOC="M32";
NET "cpu_data_b<8>" LOC="J32";
NET "cpu_data_b<7>" LOC="C34";
NET "cpu_data_b<6>" LOC="K28";
NET "cpu_data_b<5>" LOC="G30";
NET "cpu_data_b<4>" LOC="D34";
NET "cpu_data_b<3>" LOC="B34";
NET "cpu_data_b<2>" LOC="H33";
NET "cpu_data_b<1>" LOC="J26";
NET "cpu_data_b<0>" LOC="A33";
NET "pps_i" LOC="J25";
NET "pps_o" LOC="U23";
NET "dac_helper_sync_n_o" LOC="AD17";
NET "dac_helper_sclk_o" LOC="AC15";
NET "dac_helper_data_o" LOC="AH17";
NET "dac_main_sync_n_o" LOC="AM17";
NET "dac_main_sclk_o" LOC="AN17";
NET "dac_main_data_o" LOC="AP17";
NET "pll_cs_n_o" LOC="AK18";
NET "pll_sck_o" LOC="AE16";
NET "pll_mosi_o" LOC="AH19";
NET "pll_miso_i" LOC="AJ19";
NET "pll_reset_n_o" LOC="AL16";
NET "pll_status_i" LOC="AE18";
NET "pll_sync_n_o" LOC="AG18";
NET "uart_txd_o" LOC="AG31";
NET "uart_rxd_i" LOC="AC25";
NET "clk_en_o" LOC="AD16";
NET "clk_sel_o" LOC="AK17";
NET "gtx0_3_clk_n_i" LOC="AK5";
NET "gtx0_3_clk_p_i" LOC="AK6";
NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx4_7_clk_n_i" LOC="AD5";
NET "gtx4_7_clk_p_i" LOC="AD6";
NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25";
NET "gtx4_7_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx_rxp_i[0]" LOC="AP5";
NET "gtx_rxn_i[0]" LOC="AP6";
NET "gtx_txp_o[0]" LOC="AP1";
NET "gtx_txn_o[0]" LOC="AP2";
NET "gtx_rxp_i[1]" LOC="AM5";
NET "gtx_rxn_i[1]" LOC="AM6";
NET "gtx_txp_o[1]" LOC="AN3";
NET "gtx_txn_o[1]" LOC="AN4";
NET "gtx_rxp_i[2]" LOC="AL3";
NET "gtx_rxn_i[2]" LOC="AL4";
NET "gtx_txp_o[2]" LOC="AM1";
NET "gtx_txn_o[2]" LOC="AM2";
NET "gtx_rxp_i[3]" LOC="AJ3";
NET "gtx_rxn_i[3]" LOC="AJ4";
NET "gtx_txp_o[3]" LOC="AK1";
NET "gtx_txn_o[3]" LOC="AK2";
NET "gtx_rxp_i[4]" LOC="AG3";
NET "gtx_rxn_i[4]" LOC="AG4";
NET "gtx_txp_o[4]" LOC="AH1";
NET "gtx_txn_o[4]" LOC="AH2";
NET "gtx_rxp_i[5]" LOC="AF5";
NET "gtx_rxn_i[5]" LOC="AF6";
NET "gtx_txp_o[5]" LOC="AF1";
NET "gtx_txn_o[5]" LOC="AF2";
NET "mbl_scl_b" LOC="AG32"; #GPIO36
NET "mbl_sda_b" LOC="AF31"; #GPIO37
NET "gtx_sfp_tx_dis_o[0]" LOC="AD29";
NET "gtx_sfp_tx_dis_o[1]" LOC="AA29";
NET "gtx_sfp_tx_dis_o[2]" LOC="AC29";
NET "gtx_sfp_tx_dis_o[3]" LOC="AD31"; #GPIO30
NET "gtx_sfp_tx_dis_o[4]" LOC="AC28"; #GPIO33
#NET "gtx_sfp_tx_dis_o[5]" LOC="AG32"; #GPIO36
NET "led_link_o[0]" LOC="AA26"; #GPIO14
NET "led_link_o[1]" LOC="AC30"; #GPIO13
NET "led_link_o[2]" LOC="AA31"; #GPIO11
NET "led_link_o[3]" LOC="AA34"; #GPIO9
NET "led_link_o[4]" LOC="AB33"; #GPIO7
NET "led_link_o[5]" LOC="AC33"; #GPIO5
NET "led_act_o[0]" LOC="AA28"; #GPIO15
NET "led_act_o[1]" LOC="AB30"; #GPIO12
NET "led_act_o[2]" LOC="AA33"; #GPIO10
NET "led_act_o[3]" LOC="AB32"; #GPIO8
NET "led_act_o[4]" LOC="AC34"; #GPIO6
NET "led_act_o[5]" LOC="AD34"; #GPIO4
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/22
NET "fpga_clk_25mhz_n_i" TNM_NET = fpga_clk_25mhz_n_i;
TIMESPEC TS_fpga_clk_25mhz_n_i = PERIOD "fpga_clk_25mhz_n_i" 40 ns HIGH 50%;
NET "fpga_clk_25mhz_p_i" TNM_NET = fpga_clk_25mhz_p_i;
TIMESPEC TS_fpga_clk_25mhz_p_i = PERIOD "fpga_clk_25mhz_p_i" 40 ns HIGH 50%;
NET "fpga_clk_dmtd_n_i" TNM_NET = fpga_clk_dmtd_n_i;
TIMESPEC TS_fpga_clk_dmtd_n_i = PERIOD "fpga_clk_dmtd_n_i" 16 ns HIGH 50%;
NET "fpga_clk_dmtd_p_i" TNM_NET = fpga_clk_dmtd_p_i;
TIMESPEC TS_fpga_clk_dmtd_p_i = PERIOD "fpga_clk_dmtd_p_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_n_i" TNM_NET = fpga_clk_ref_n_i;
TIMESPEC TS_fpga_clk_ref_n_i = PERIOD "fpga_clk_ref_n_i" 16 ns HIGH 50%;
NET "fpga_clk_ref_p_i" TNM_NET = fpga_clk_ref_p_i;
TIMESPEC TS_fpga_clk_ref_p_i = PERIOD "fpga_clk_ref_p_i" 16 ns HIGH 50%;
NET "fpga_clk_aux_n_i" TNM_NET = fpga_clk_aux_n_i;
TIMESPEC TS_fpga_clk_aux_n_i = PERIOD "fpga_clk_aux_n_i" 5 ns HIGH 50%;
NET "fpga_clk_aux_p_i" TNM_NET = fpga_clk_aux_p_i;
TIMESPEC TS_fpga_clk_aux_p_i = PERIOD "fpga_clk_aux_p_i" 5 ns HIGH 50%;
NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_1__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[1].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[3].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[4].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[4].U_PHY/tx_out_clk_bufin;
TIMESPEC TS_gen_phys_4__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[4].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[0].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[0].U_PHY/tx_out_clk_bufin;
TIMESPEC TS_gen_phys_0__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[0].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[2].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[5].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_5__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[4].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i;
TIMESPEC TS_gtx0_3_clk_n_i = PERIOD "gtx0_3_clk_n_i" 8 ns HIGH 50%;
NET "gtx0_3_clk_p_i" TNM_NET = gtx0_3_clk_p_i;
TIMESPEC TS_gtx0_3_clk_p_i = PERIOD "gtx0_3_clk_p_i" 8 ns HIGH 50%;
NET "gtx4_7_clk_p_i" TNM_NET = gtx4_7_clk_p_i;
TIMESPEC TS_gtx4_7_clk_p_i = PERIOD "gtx4_7_clk_p_i" 8 ns HIGH 50%;
NET "gtx4_7_clk_n_i" TNM_NET = gtx4_7_clk_n_i;
TIMESPEC TS_gtx4_7_clk_n_i = PERIOD "gtx4_7_clk_n_i" 8 ns HIGH 50%;
top/scb_6ports_omb/scb_top_synthesis.vhd deleted 100644 → 0
View file @ a7384a41
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