.gitlab-ci.yml: add CI from commit 73ed763b

.gitlab-ci.yml copied from based on commit 73ed763bSigned-off-by: Adam Wujek <dev_public@wujek.eu>

.gitlab-ci.yml: add CI from commit 73ed763b
.gitlab-ci.yml copied from based on commit 73ed763bSigned-off-by: Adam Wujek <dev_public@wujek.eu>
7fddb8cf · Adam Wujek · 9a26b13e · 7fddb8cf
Commit 7fddb8cf authored Apr 11, 2024 by Adam Wujek
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--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
+variables:
+        GIT_SUBMODULE_STRATEGY: normal
+
+stages:
+ - sim
+ - syn
+
+job_scb_top_sim:
+   stage: sim
+   when: manual
+   tags:
+    - modelsim_10.2a
+   script:
+    - /entrypoint.sh
+    - source ~/setup_modelsim.sh
+    - git submodule sync & git submodule update --init
+    - apt-get install -y python
+    - cd top/bare_top
+    - python gen_sdbsyn.py --project wr_switch
+    - cd ../../modules/wrsw_hwiu
+    - python gen_ver.py
+    - cat gw_ver_pkg.vhd
+    - cd ../../
+    - cd sim
+    - ln -s ../ip_cores/wr-cores/sim wr-hdl
+    - cd ../testbench/scb_top
+    - cp /opt/compiled_libs_ise14.7/modelsim.ini .
+    - hdlmake makefile
+    - make
+    - vsim -c -do run.do
+
+job_scb_top_8p_syn:
+   stage: syn
+   tags:
+    - xilinx_ISE_14.7 
+   script:
+    - /entrypoint.sh
+    - source ~/setup_ise147.sh
+    - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+    - cd top/bare_top
+    - python gen_sdbsyn.py --project wr_switch
+    - cat synthesis_descriptor.vhd
+    - cd ../../modules/wrsw_hwiu
+    - python gen_ver.py
+    - cat gw_ver_pkg.vhd
+    - cd ../../syn/scb_8ports 
+    - hdlmake makefile 
+    - make
+   artifacts:
+    name: SCB_TOP_8P_CI_$CI_JOB_ID
+    paths:
+    - syn/scb_8ports/*.syr
+    - syn/scb_8ports/*.mrp
+    - syn/scb_8ports/*.bit
+    - syn/scb_8ports/*.bin
+    - syn/scb_8ports/*.par
+    - syn/scb_8ports/*.twr
+
+job_scb_top_18p_syn:
+   stage: syn
+   when: manual
+   tags:
+    - xilinx_ISE_14.7 
+   script:
+    - /entrypoint.sh
+    - source ~/setup_ise147.sh
+    - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+    - cd top/bare_top
+    - python gen_sdbsyn.py --project wr_switch
+    - cat synthesis_descriptor.vhd
+    - cd ../../modules/wrsw_hwiu
+    - python gen_ver.py
+    - cat gw_ver_pkg.vhd
+    - cd ../../syn/scb_18ports 
+    - hdlmake makefile 
+    - make
+   artifacts:
+    name: SCB_TOP_18P_CI_$CI_JOB_ID
+    paths:
+    - syn/scb_18ports/*.syr
+    - syn/scb_18ports/*.mrp
+    - syn/scb_18ports/*.bit
+    - syn/scb_18ports/*.bin
+    - syn/scb_18ports/*.par
+    - syn/scb_18ports/*.twr