scb_8ports: top level with HW PWM controller for fan speed adjustment

745014ce · Tomasz Wlostowski · ea1c7152 · 745014ce · 745014ce · 745014ce
Commit 745014ce authored Jan 09, 2013 by Tomasz Wlostowski
4 changed files
--- a/syn/scb_8ports/test_scb.xise
+++ b/syn/scb_8ports/test_scb.xise
--- a/top/bare_top/scb_top_bare.vhd
+++ b/top/bare_top/scb_top_bare.vhd
@@ -87,16 +87,16 @@ entity scb_top_bare is
    -------------------------------------------------------------------------------

    -- GTX clock fanout enable
-    clk_en_o  : out std_logic;
+    clk_en_o : out std_logic;

    -- GTX clock fanout source select
    clk_sel_o : out std_logic;

    -- DMTD clock divider selection (0 = 125 MHz, 1 = 62.5 MHz)
-    clk_dmtd_divsel_o: out std_logic;
+    clk_dmtd_divsel_o : out std_logic;

    -- UART source selection (FPGA/DBGU)
-    uart_sel_o: out std_logic;
+    uart_sel_o : out std_logic;

    ---------------------------------------------------------------------------
    -- GTX ports
@@ -122,13 +122,20 @@ entity scb_top_bare is
    i2c_scl_i     : in  std_logic_vector(2 downto 0) := "111";
    i2c_sda_oen_o : out std_logic_vector(2 downto 0);
    i2c_sda_o     : out std_logic_vector(2 downto 0);
-    i2c_sda_i     : in  std_logic_vector(2 downto 0) := "111"
+    i2c_sda_i     : in  std_logic_vector(2 downto 0) := "111";
+
+    ---------------------------------------------------------------------------
+    -- Mini-backplane PWM fans
+    ---------------------------------------------------------------------------
+
+    mb_fan1_pwm_o : out std_logic;
+    mb_fan2_pwm_o : out std_logic
    );
 end scb_top_bare;

 architecture rtl of scb_top_bare is

-  constant c_NUM_WB_SLAVES : integer := 10;
+  constant c_NUM_WB_SLAVES : integer := 11;
  constant c_NUM_PORTS     : integer := g_num_ports;
  constant c_MAX_PORTS     : integer := 18;

@@ -146,10 +153,12 @@ architecture rtl of scb_top_bare is
  constant c_SLAVE_GPIO         : integer := 6;
  constant c_SLAVE_MBL_I2C0     : integer := 7;
  constant c_SLAVE_MBL_I2C1     : integer := 8;
-  constant c_SLAVE_SENSOR_I2C     : integer := 9;
+  constant c_SLAVE_SENSOR_I2C   : integer := 9;
+  constant c_SLAVE_PWM          : integer := 10;

  constant c_cnx_base_addr : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
    (
+      x"00057000",                      -- PWM Controller
      x"00056000",                      -- Sensors-I2C
      x"00055000",                      -- MBL-I2C1
      x"00054000",                      -- MBL-I2C0
@@ -164,6 +173,7 @@ architecture rtl of scb_top_bare is

  constant c_cnx_base_mask : t_wishbone_address_array(c_NUM_WB_SLAVES-1 downto 0) :=
    (x"000ff000",
+     x"000ff000",
     x"000ff000",
     x"000ff000",
     x"000ff000",
@@ -555,7 +565,7 @@ begin
    end generate gen_terminate_unused_eps;


-    gen_txtsu_debug: for i in 0 to c_NUM_PORTS-1 generate
+    gen_txtsu_debug : for i in 0 to c_NUM_PORTS-1 generate
      TRIG0(i) <= txtsu_timestamps(i).stb;
      trig1(i) <= txtsu_timestamps_ack(i);
      trig2(0) <= vic_irqs(0);
@@ -578,7 +588,7 @@ begin
        g_wb_ob_ignore_ack                => false,
        g_mpm_mem_size                    => 67584,
        g_mpm_page_size                   => 66,
-        g_mpm_ratio                       => 6, --f_swc_ratio,  --2
+        g_mpm_ratio                       => 6,  --f_swc_ratio,  --2
        g_mpm_fifo_size                   => 8,
        g_mpm_fetch_next_pg_in_advance    => false)
      port map (
@@ -676,7 +686,7 @@ begin

  uart_sel_o <= gpio_out(31);

-  
+
  gpio_o <= gpio_out;

  U_MiniBackplane_I2C0 : xwb_i2c_master
@@ -730,6 +740,23 @@ begin
      sda_pad_o    => i2c_sda_o(2),
      sda_padoen_o => i2c_sda_oen_o(2));

+  -----------------------------------------------------------------------------
+  -- PWM Controlle for mini-backplane fan drive
+  -----------------------------------------------------------------------------
+  
+  U_PWM_Controller : xwb_simple_pwm
+    generic map (
+      g_num_channels        => 2,
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => BYTE)
+    port map (
+      clk_sys_i => clk_sys,
+      rst_n_i   => rst_n_periph,
+      slave_i   => cnx_master_out(c_SLAVE_PWM),
+      slave_o   => cnx_master_in(c_SLAVE_PWM),
+      pwm_o(0)  => mb_fan1_pwm_o,
+      pwm_o(1)  => mb_fan2_pwm_o);
+
  -----------------------------------------------------------------------------
  -- Interrupt assignment
  -----------------------------------------------------------------------------
@@ -743,9 +770,9 @@ begin
 -- Various constant-driven I/Os
 -------------------------------------------------------------------------------

-  clk_en_o  <= '0';
-  clk_sel_o <= '0';
+  clk_en_o          <= '0';
+  clk_sel_o         <= '0';
  clk_dmtd_divsel_o <= '1';             -- choose 62.5 MHz DDMTD clock
-  clk_sys_o <= clk_sys;
+  clk_sys_o         <= clk_sys;
  
 end rtl;
--- a/top/scb_8ports/scb_top_synthesis.ucf
+++ b/top/scb_8ports/scb_top_synthesis.ucf
@@ -260,7 +260,6 @@ NET "led_act_o[6]" LOC="AB27";
 NET "led_act_o[7]" LOC="AC27";  

 NET "clk_dmtd_divsel_o" LOC="AN15";
-NET "uart_sel_o" LOC="C12";


 NET "mbl_scl_b[0]" LOC="AF31"; 
@@ -268,6 +267,9 @@ NET "mbl_sda_b[0]" LOC="AG32";
 NET "mbl_scl_b[1]" LOC="AC25"; 
 NET "mbl_sda_b[1]" LOC="AG31"; 

+NET "mb_fan1_pwm_o" LOC="C12";
+NET "mb_fan2_pwm_o" LOC="D12";
+
 #Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/20
 #Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/01/22
 NET "fpga_clk_25mhz_n_i" TNM_NET = fpga_clk_25mhz_n_i;

--- a/top/scb_8ports/scb_top_synthesis.vhd
+++ b/top/scb_8ports/scb_top_synthesis.vhd
@@ -103,7 +103,7 @@ entity scb_top_synthesis is
    clk_dmtd_divsel_o : out std_logic;

    -- UART source selection (FPGA/DBGU)
-    uart_sel_o : out std_logic;
+    -- uart_sel_o : out std_logic;

    ---------------------------------------------------------------------------
    -- GTX ports
@@ -146,7 +146,10 @@ entity scb_top_synthesis is
    mbl_sda_b : inout std_logic_vector(1 downto 0);

    sensors_scl_b: inout std_logic;
-    sensors_sda_b: inout std_logic
+    sensors_sda_b: inout std_logic;
+
+    mb_fan1_pwm_o : out std_logic;
+    mb_fan2_pwm_o : out std_logic
  );

 end scb_top_synthesis;
@@ -271,7 +274,10 @@ architecture Behavioral of scb_top_synthesis is
      i2c_scl_i       : in  std_logic_vector(2 downto 0) := "111";
      i2c_sda_oen_o   : out std_logic_vector(2 downto 0);
      i2c_sda_o       : out std_logic_vector(2 downto 0);
-      i2c_sda_i       : in  std_logic_vector(2 downto 0) := "111");
+      i2c_sda_i       : in  std_logic_vector(2 downto 0) := "111";
+      mb_fan1_pwm_o : out std_logic;
+      mb_fan2_pwm_o : out std_logic
+      );
  end component;

  component chipscope_icon
@@ -579,7 +585,7 @@ begin
      uart_rxd_i          => uart_rxd_i,
      clk_en_o            => clk_en_o,
      clk_sel_o           => clk_sel_o,
-      uart_sel_o          => uart_sel_o,
+--      uart_sel_o          => uart_sel_o,
      clk_dmtd_divsel_o   => clk_dmtd_divsel_o,
      gpio_i              => x"00000000",
      phys_o              => to_phys(c_NUM_PORTS-1 downto 0),
@@ -591,7 +597,9 @@ begin
      i2c_scl_i       => i2c_scl_in,
      i2c_sda_oen_o   => i2c_sda_oen,
      i2c_sda_o       => i2c_sda_out,
-      i2c_sda_i       => i2c_sda_in);
+      i2c_sda_i       => i2c_sda_in,
+      mb_fan1_pwm_o => mb_fan1_pwm_o,
+      mb_fan2_pwm_o => mb_fan2_pwm_o);

  i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
  i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);