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White Rabbit Switch - Gateware
Commit 6b3c0e71 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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wrsw_rt_subsystem: allow externally sampled RX clocks (DDMTD inside the PHY module)

parent 205a4500
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modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 6b3c0e71
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2012-01-10 -- Created : 2012-01-10
-- Last update: 2014-02-06 -- Last update: 2017-06-22
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -45,21 +45,23 @@ use work.wrs_sdb_pkg.all; ...@@ -45,21 +45,23 @@ use work.wrs_sdb_pkg.all;
entity wrsw_rt_subsystem is entity wrsw_rt_subsystem is
generic ( generic (
g_num_rx_clocks : integer; g_num_rx_clocks : integer;
g_num_ext_clks : integer; g_num_ext_clks : integer;
g_simulation : boolean); g_simulation : boolean;
g_use_sampled_rx_clocks : boolean);
port( port(
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0); clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic; clk_rx_sampled_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0); clk_ext_i : in std_logic;
clk_ext_mul_locked_i : in std_logic; clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_aux_p_o : out std_logic; clk_ext_mul_locked_i : in std_logic;
clk_aux_n_o : out std_logic; clk_aux_p_o : out std_logic;
clk_500_o : out std_logic; clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
rst_sys_n_i : in std_logic; rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic; rst_ref_n_i : in std_logic;
...@@ -108,7 +110,7 @@ entity wrsw_rt_subsystem is ...@@ -108,7 +110,7 @@ entity wrsw_rt_subsystem is
-- Wired to IODelay in the top module for precise 1-PPS out alignment -- Wired to IODelay in the top module for precise 1-PPS out alignment
-- with clk_aux -- with clk_aux
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0'); ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others => '0');
ppsdel_tap_o : out std_logic_vector(4 downto 0); ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic; ppsdel_tap_wr_o : out std_logic;
...@@ -145,7 +147,7 @@ entity wrsw_rt_subsystem is ...@@ -145,7 +147,7 @@ entity wrsw_rt_subsystem is
ljd_pll_locked_i : in std_logic; ljd_pll_locked_i : in std_logic;
-- Debug -- Debug
spll_dbg_o : out std_logic_vector(5 downto 0) spll_dbg_o : out std_logic_vector(5 downto 0)
); );
end wrsw_rt_subsystem; end wrsw_rt_subsystem;
...@@ -153,17 +155,18 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -153,17 +155,18 @@ architecture rtl of wrsw_rt_subsystem is
component xwr_softpll_ng component xwr_softpll_ng
generic ( generic (
g_tag_bits : integer; g_tag_bits : integer;
g_num_ref_inputs : integer; g_num_ref_inputs : integer;
g_num_outputs : integer; g_num_outputs : integer;
g_num_exts : integer; g_num_exts : integer;
g_with_debug_fifo : boolean; g_with_debug_fifo : boolean;
g_divide_input_by_2 : boolean; g_divide_input_by_2 : boolean;
g_reverse_dmtds : boolean; g_reverse_dmtds : boolean;
g_ref_clock_rate : integer; g_ref_clock_rate : integer;
g_ext_clock_rate : integer; g_ext_clock_rate : integer;
g_interface_mode : t_wishbone_interface_mode; g_use_sampled_ref_clocks : boolean;
g_address_granularity : t_wishbone_address_granularity); g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port ( port (
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic; rst_sys_n_i : in std_logic;
...@@ -171,6 +174,7 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -171,6 +174,7 @@ architecture rtl of wrsw_rt_subsystem is
rst_ext_n_i : in std_logic; rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic; rst_dmtd_n_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0); clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_ref_sampled_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0); clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic; clk_ext_i : in std_logic;
...@@ -198,18 +202,18 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -198,18 +202,18 @@ architecture rtl of wrsw_rt_subsystem is
g_interface_mode : t_wishbone_interface_mode := PIPELINED; g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD); g_address_granularity : t_wishbone_address_granularity := WORD);
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
clk_i : in std_logic; clk_i : in std_logic;
pps_i : in std_logic; pps_i : in std_logic;
pps_valid_i : in std_logic; pps_valid_i : in std_logic;
clk_aux_p_o : out std_logic; clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic; clk_aux_n_o : out std_logic;
clk_500_o : out std_logic; clk_500_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0); ppsdel_tap_i : in std_logic_vector(4 downto 0);
ppsdel_tap_o : out std_logic_vector(4 downto 0); ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic; ppsdel_tap_wr_o : out std_logic;
slave_i : in t_wishbone_slave_in; slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out); slave_o : out t_wishbone_slave_out);
end component; end component;
...@@ -224,8 +228,8 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -224,8 +228,8 @@ architecture rtl of wrsw_rt_subsystem is
constant c_NUM_GPIO_PINS : integer := 9; constant c_NUM_GPIO_PINS : integer := 9;
constant c_NUM_WB_SLAVES : integer := 9; constant c_NUM_WB_SLAVES : integer := 9;
constant c_MASTER_CPU : integer := 0; constant c_MASTER_CPU : integer := 0;
constant c_MASTER_LM32 : integer := 1; constant c_MASTER_LM32 : integer := 1;
constant c_SLAVE_DPRAM : integer := 0; constant c_SLAVE_DPRAM : integer := 0;
constant c_SLAVE_UART : integer := 1; constant c_SLAVE_UART : integer := 1;
...@@ -254,9 +258,9 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -254,9 +258,9 @@ architecture rtl of wrsw_rt_subsystem is
signal dac_out_data, dac_dmtd_data : std_logic_vector(15 downto 0); signal dac_out_data, dac_dmtd_data : std_logic_vector(15 downto 0);
signal dac_out_load, dac_dmtd_load : std_logic; signal dac_out_load, dac_dmtd_load : std_logic;
signal clk_rx_vec : std_logic_vector(g_num_rx_clocks-1 downto 0); signal clk_rx_vec, clk_rx_sampled_vec : std_logic_vector(g_num_rx_clocks-1 downto 0);
signal pps_csync : std_logic; signal pps_csync : std_logic;
signal pps_valid : std_logic; signal pps_valid : std_logic;
function f_pick ( function f_pick (
cond : boolean; cond : boolean;
...@@ -277,7 +281,8 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -277,7 +281,8 @@ architecture rtl of wrsw_rt_subsystem is
begin -- rtl begin -- rtl
clk_rx_vec(g_num_rx_clocks-1 downto 0) <= clk_rx_i; clk_rx_vec(g_num_rx_clocks-1 downto 0) <= clk_rx_i;
clk_rx_sampled_vec(g_num_rx_clocks-1 downto 0) <= clk_rx_sampled_i;
cnx_slave_in(c_MASTER_CPU) <= wb_i; cnx_slave_in(c_MASTER_CPU) <= wb_i;
wb_o <= cnx_slave_out(c_MASTER_CPU); wb_o <= cnx_slave_out(c_MASTER_CPU);
...@@ -344,23 +349,25 @@ begin -- rtl ...@@ -344,23 +349,25 @@ begin -- rtl
U_SoftPLL : xwr_softpll_ng U_SoftPLL : xwr_softpll_ng
generic map ( generic map (
g_tag_bits => 22, g_tag_bits => 22,
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE, g_address_granularity => BYTE,
g_num_ref_inputs => g_num_rx_clocks, g_num_ref_inputs => g_num_rx_clocks,
g_num_outputs => 1, g_num_outputs => 1,
g_num_exts => g_num_ext_clks, g_num_exts => g_num_ext_clks,
g_reverse_dmtds => true, g_reverse_dmtds => true,
g_divide_input_by_2 => false, g_divide_input_by_2 => false,
g_with_debug_fifo => true, g_with_debug_fifo => true,
g_ref_clock_rate => 62500000, g_ref_clock_rate => 62500000,
g_ext_clock_rate => 10000000) g_ext_clock_rate => 10000000,
g_use_sampled_ref_clocks => g_use_sampled_rx_clocks)
port map ( port map (
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i, rst_sys_n_i => rst_sys_n_i,
rst_ref_n_i => rst_ref_n_i, rst_ref_n_i => rst_ref_n_i,
rst_ext_n_i => rst_ext_n_i, rst_ext_n_i => rst_ext_n_i,
rst_dmtd_n_i => rst_dmtd_n_i, rst_dmtd_n_i => rst_dmtd_n_i,
clk_ref_sampled_i => clk_rx_sampled_vec,
clk_ref_i => clk_rx_vec, clk_ref_i => clk_rx_vec,
clk_fb_i(0) => clk_ref_i, clk_fb_i(0) => clk_ref_i,
clk_dmtd_i => clk_dmtd_i, clk_dmtd_i => clk_dmtd_i,
...@@ -406,7 +413,7 @@ begin -- rtl ...@@ -406,7 +413,7 @@ begin -- rtl
tm_cycles_o => tm_cycles_o, tm_cycles_o => tm_cycles_o,
tm_time_valid_o => tm_time_valid_o); tm_time_valid_o => tm_time_valid_o);
pps_csync_o <= pps_csync; pps_csync_o <= pps_csync;
pps_valid_o <= pps_valid; pps_valid_o <= pps_valid;
cpu_irq_vec(31 downto 1) <= (others => '0'); cpu_irq_vec(31 downto 1) <= (others => '0');
...@@ -476,8 +483,8 @@ begin -- rtl ...@@ -476,8 +483,8 @@ begin -- rtl
slave_i => cnx_master_out(c_SLAVE_TIMER), slave_i => cnx_master_out(c_SLAVE_TIMER),
slave_o => cnx_master_in(c_SLAVE_TIMER), slave_o => cnx_master_in(c_SLAVE_TIMER),
desc_o => open); desc_o => open);
U_GEN_10_MHZ: xwrsw_gen_10mhz U_GEN_10_MHZ : xwrsw_gen_10mhz
generic map ( generic map (
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE) g_address_granularity => BYTE)
...@@ -492,8 +499,8 @@ begin -- rtl ...@@ -492,8 +499,8 @@ begin -- rtl
ppsdel_tap_i => ppsdel_tap_i, ppsdel_tap_i => ppsdel_tap_i,
ppsdel_tap_o => ppsdel_tap_o, ppsdel_tap_o => ppsdel_tap_o,
ppsdel_tap_wr_o => ppsdel_tap_wr_o, ppsdel_tap_wr_o => ppsdel_tap_wr_o,
slave_i => cnx_master_out(c_SLAVE_GEN10), slave_i => cnx_master_out(c_SLAVE_GEN10),
slave_o => cnx_master_in(c_SLAVE_GEN10)); slave_o => cnx_master_in(c_SLAVE_GEN10));
sel_clk_sys_o <= gpio_out(0); sel_clk_sys_o <= gpio_out(0);
pll_reset_n_o <= gpio_out(1); pll_reset_n_o <= gpio_out(1);
......
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