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White Rabbit Switch - Gateware
Commit 5d5f1a74 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'greg-lpd-rebased' into proposed_master

parents 205a4500 868072d9
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Manifest.py
View file @ 5d5f1a74
...@@ -5,8 +5,8 @@ modules = { "local" : [ ...@@ -5,8 +5,8 @@ modules = { "local" : [
"modules/wrsw_tru", "modules/wrsw_tru",
"modules/wrsw_tatsu", "modules/wrsw_tatsu",
"modules/wrsw_pstats", "modules/wrsw_pstats",
"modules/wrsw_hwiu", "modules/wrsw_hwiu",
"modules/wrsw_watchdog", "modules/wrsw_watchdog",
"platform/virtex6/chipscope", "platform/virtex6/chipscope",
"platform/xilinx", "platform/xilinx",
"ip_cores/wr-cores", "ip_cores/wr-cores",
......
general-cores @ dcc7cc33
Subproject commit 17d08e592c482848bf1ce9401f39a2a8749d04f4 Subproject commit dcc7cc33ffa3bce1a9a3da9ea317e3c768830398
wr-cores @ 25deb517
Subproject commit b23b87769f895a8f75402ac47b401bf02bff6a57 Subproject commit 25deb51759cf467df4fdeeca3bd10e4e793f71ca
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 5d5f1a74
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski -- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2012-01-10 -- Created : 2012-01-10
-- Last update: 2014-02-06 -- Last update: 2018-11-07
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -40,26 +40,29 @@ use ieee.std_logic_1164.all; ...@@ -40,26 +40,29 @@ use ieee.std_logic_1164.all;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
use work.wrs_sdb_pkg.all; use work.wrs_sdb_pkg.all;
use work.wrsw_shared_types_pkg.all;
entity wrsw_rt_subsystem is entity wrsw_rt_subsystem is
generic ( generic (
g_num_rx_clocks : integer; g_num_rx_clocks : integer;
g_num_ext_clks : integer; g_num_ext_clks : integer;
g_simulation : boolean); g_simulation : boolean;
g_phy_lpcalib : t_bool_array(0 to 17));
port( port(
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0); clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic; clk_rx_sampled_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0); clk_ext_i : in std_logic;
clk_ext_mul_locked_i : in std_logic; clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_aux_p_o : out std_logic; clk_ext_mul_locked_i : in std_logic;
clk_aux_n_o : out std_logic; clk_aux_p_o : out std_logic;
clk_500_o : out std_logic; clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
rst_sys_n_i : in std_logic; rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic; rst_ref_n_i : in std_logic;
...@@ -108,7 +111,7 @@ entity wrsw_rt_subsystem is ...@@ -108,7 +111,7 @@ entity wrsw_rt_subsystem is
-- Wired to IODelay in the top module for precise 1-PPS out alignment -- Wired to IODelay in the top module for precise 1-PPS out alignment
-- with clk_aux -- with clk_aux
ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others=>'0'); ppsdel_tap_i : in std_logic_vector(4 downto 0) := (others => '0');
ppsdel_tap_o : out std_logic_vector(4 downto 0); ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic; ppsdel_tap_wr_o : out std_logic;
...@@ -145,71 +148,29 @@ entity wrsw_rt_subsystem is ...@@ -145,71 +148,29 @@ entity wrsw_rt_subsystem is
ljd_pll_locked_i : in std_logic; ljd_pll_locked_i : in std_logic;
-- Debug -- Debug
spll_dbg_o : out std_logic_vector(5 downto 0) spll_dbg_o : out std_logic_vector(5 downto 0)
); );
end wrsw_rt_subsystem; end wrsw_rt_subsystem;
architecture rtl of wrsw_rt_subsystem is architecture rtl of wrsw_rt_subsystem is
component xwr_softpll_ng
generic (
g_tag_bits : integer;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_num_exts : integer;
g_with_debug_fifo : boolean;
g_divide_input_by_2 : boolean;
g_reverse_dmtds : boolean;
g_ref_clock_rate : integer;
g_ext_clock_rate : integer;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_exts-1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_ext_rst_o : out std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
dac_dmtd_load_o : out std_logic;
dac_out_data_o : out std_logic_vector(15 downto 0);
dac_out_sel_o : out std_logic_vector(3 downto 0);
dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic);
end component;
component xwrsw_gen_10mhz component xwrsw_gen_10mhz
generic ( generic (
g_interface_mode : t_wishbone_interface_mode := PIPELINED; g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD); g_address_granularity : t_wishbone_address_granularity := WORD);
port ( port (
rst_n_i : in std_logic; rst_n_i : in std_logic;
clk_i : in std_logic; clk_i : in std_logic;
pps_i : in std_logic; pps_i : in std_logic;
pps_valid_i : in std_logic; pps_valid_i : in std_logic;
clk_aux_p_o : out std_logic; clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic; clk_aux_n_o : out std_logic;
clk_500_o : out std_logic; clk_500_o : out std_logic;
ppsdel_tap_i : in std_logic_vector(4 downto 0); ppsdel_tap_i : in std_logic_vector(4 downto 0);
ppsdel_tap_o : out std_logic_vector(4 downto 0); ppsdel_tap_o : out std_logic_vector(4 downto 0);
ppsdel_tap_wr_o : out std_logic; ppsdel_tap_wr_o : out std_logic;
slave_i : in t_wishbone_slave_in; slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out); slave_o : out t_wishbone_slave_out);
end component; end component;
...@@ -224,8 +185,8 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -224,8 +185,8 @@ architecture rtl of wrsw_rt_subsystem is
constant c_NUM_GPIO_PINS : integer := 9; constant c_NUM_GPIO_PINS : integer := 9;
constant c_NUM_WB_SLAVES : integer := 9; constant c_NUM_WB_SLAVES : integer := 9;
constant c_MASTER_CPU : integer := 0; constant c_MASTER_CPU : integer := 0;
constant c_MASTER_LM32 : integer := 1; constant c_MASTER_LM32 : integer := 1;
constant c_SLAVE_DPRAM : integer := 0; constant c_SLAVE_DPRAM : integer := 0;
constant c_SLAVE_UART : integer := 1; constant c_SLAVE_UART : integer := 1;
...@@ -254,9 +215,9 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -254,9 +215,9 @@ architecture rtl of wrsw_rt_subsystem is
signal dac_out_data, dac_dmtd_data : std_logic_vector(15 downto 0); signal dac_out_data, dac_dmtd_data : std_logic_vector(15 downto 0);
signal dac_out_load, dac_dmtd_load : std_logic; signal dac_out_load, dac_dmtd_load : std_logic;
signal clk_rx_vec : std_logic_vector(g_num_rx_clocks-1 downto 0); signal clk_rx_vec, clk_rx_sampled_vec : std_logic_vector(g_num_rx_clocks-1 downto 0);
signal pps_csync : std_logic; signal pps_csync : std_logic;
signal pps_valid : std_logic; signal pps_valid : std_logic;
function f_pick ( function f_pick (
cond : boolean; cond : boolean;
...@@ -277,7 +238,7 @@ architecture rtl of wrsw_rt_subsystem is ...@@ -277,7 +238,7 @@ architecture rtl of wrsw_rt_subsystem is
begin -- rtl begin -- rtl
clk_rx_vec(g_num_rx_clocks-1 downto 0) <= clk_rx_i; clk_rx_vec(g_num_rx_clocks-1 downto 0) <= clk_rx_i;
cnx_slave_in(c_MASTER_CPU) <= wb_i; cnx_slave_in(c_MASTER_CPU) <= wb_i;
wb_o <= cnx_slave_out(c_MASTER_CPU); wb_o <= cnx_slave_out(c_MASTER_CPU);
...@@ -342,25 +303,49 @@ begin -- rtl ...@@ -342,25 +303,49 @@ begin -- rtl
uart_txd_o => uart_txd_o); uart_txd_o => uart_txd_o);
U_SoftPLL : xwr_softpll_ng -----------------------------------------------------------------------------
-- External sampler for rx clocks coming from GTX-es that are not
-- calibrated for low phase drift
-----------------------------------------------------------------------------
gen_Samplers: for I in 0 to g_num_rx_clocks-1 generate
gen_lp: if g_phy_lpcalib(I) generate
clk_rx_sampled_vec(I) <= clk_rx_sampled_i(I);
end generate gen_lp;
gen_no_lp: if not g_phy_lpcalib(I) generate
U_Sampler: entity work.dmtd_sampler
generic map (
g_divide_input_by_2 => false,
g_reverse => true)
port map (
clk_in_i => clk_rx_vec(I),
clk_dmtd_i => clk_dmtd_i,
clk_sampled_o => clk_rx_sampled_vec(I));
end generate gen_no_lp;
end generate gen_Samplers;
-----------------------------------------------------------------------------
U_SoftPLL : entity work.xwr_softpll_ng
generic map ( generic map (
g_tag_bits => 22, g_tag_bits => 22,
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE, g_address_granularity => BYTE,
g_num_ref_inputs => g_num_rx_clocks, g_num_ref_inputs => g_num_rx_clocks,
g_num_outputs => 1, g_num_outputs => 1,
g_num_exts => g_num_ext_clks, g_num_exts => g_num_ext_clks,
g_reverse_dmtds => true, g_reverse_dmtds => true,
g_divide_input_by_2 => false, g_divide_input_by_2 => false,
g_with_debug_fifo => true, g_with_debug_fifo => true,
g_ref_clock_rate => 62500000, g_ref_clock_rate => 62500000,
g_ext_clock_rate => 10000000) g_ext_clock_rate => 10000000,
g_use_sampled_ref_clocks => true)
port map ( port map (
clk_sys_i => clk_sys_i, clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i, rst_sys_n_i => rst_sys_n_i,
rst_ref_n_i => rst_ref_n_i, rst_ref_n_i => rst_ref_n_i,
rst_ext_n_i => rst_ext_n_i, rst_ext_n_i => rst_ext_n_i,
rst_dmtd_n_i => rst_dmtd_n_i, rst_dmtd_n_i => rst_dmtd_n_i,
clk_ref_sampled_i => clk_rx_sampled_vec,
clk_ref_i => clk_rx_vec, clk_ref_i => clk_rx_vec,
clk_fb_i(0) => clk_ref_i, clk_fb_i(0) => clk_ref_i,
clk_dmtd_i => clk_dmtd_i, clk_dmtd_i => clk_dmtd_i,
...@@ -406,7 +391,7 @@ begin -- rtl ...@@ -406,7 +391,7 @@ begin -- rtl
tm_cycles_o => tm_cycles_o, tm_cycles_o => tm_cycles_o,
tm_time_valid_o => tm_time_valid_o); tm_time_valid_o => tm_time_valid_o);
pps_csync_o <= pps_csync; pps_csync_o <= pps_csync;
pps_valid_o <= pps_valid; pps_valid_o <= pps_valid;
cpu_irq_vec(31 downto 1) <= (others => '0'); cpu_irq_vec(31 downto 1) <= (others => '0');
...@@ -476,8 +461,8 @@ begin -- rtl ...@@ -476,8 +461,8 @@ begin -- rtl
slave_i => cnx_master_out(c_SLAVE_TIMER), slave_i => cnx_master_out(c_SLAVE_TIMER),
slave_o => cnx_master_in(c_SLAVE_TIMER), slave_o => cnx_master_in(c_SLAVE_TIMER),
desc_o => open); desc_o => open);
U_GEN_10_MHZ: xwrsw_gen_10mhz U_GEN_10_MHZ : xwrsw_gen_10mhz
generic map ( generic map (
g_interface_mode => PIPELINED, g_interface_mode => PIPELINED,
g_address_granularity => BYTE) g_address_granularity => BYTE)
...@@ -492,8 +477,8 @@ begin -- rtl ...@@ -492,8 +477,8 @@ begin -- rtl
ppsdel_tap_i => ppsdel_tap_i, ppsdel_tap_i => ppsdel_tap_i,
ppsdel_tap_o => ppsdel_tap_o, ppsdel_tap_o => ppsdel_tap_o,
ppsdel_tap_wr_o => ppsdel_tap_wr_o, ppsdel_tap_wr_o => ppsdel_tap_wr_o,
slave_i => cnx_master_out(c_SLAVE_GEN10), slave_i => cnx_master_out(c_SLAVE_GEN10),
slave_o => cnx_master_in(c_SLAVE_GEN10)); slave_o => cnx_master_in(c_SLAVE_GEN10));
sel_clk_sys_o <= gpio_out(0); sel_clk_sys_o <= gpio_out(0);
pll_reset_n_o <= gpio_out(1); pll_reset_n_o <= gpio_out(1);
......
modules/wrsw_shared_types_pkg.vhd
View file @ 5d5f1a74
...@@ -39,6 +39,9 @@ package wrsw_shared_types_pkg is ...@@ -39,6 +39,9 @@ package wrsw_shared_types_pkg is
constant c_RTU_MAX_PORTS : integer := 32; constant c_RTU_MAX_PORTS : integer := 32;
constant c_SWC_MAX_PORTS : integer := c_RTU_MAX_PORTS+1; constant c_SWC_MAX_PORTS : integer := c_RTU_MAX_PORTS+1;
type t_bool_array is array(integer range <>) of boolean;
constant c_BOOL_FALSE_ARRAY : t_bool_array(0 to 17) := (others=>false);
type t_rtu_request is record type t_rtu_request is record
valid : std_logic; valid : std_logic;
smac : std_logic_vector(47 downto 0); smac : std_logic_vector(47 downto 0);
......
top/bare_top/scb_top_bare.vhd
View file @ 5d5f1a74
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk -- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2012-02-21 -- Created : 2012-02-21
-- Last update: 2014-03-17 -- Last update: 2018-11-07
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -64,7 +64,8 @@ entity scb_top_bare is ...@@ -64,7 +64,8 @@ entity scb_top_bare is
g_with_PSTATS : boolean := true; g_with_PSTATS : boolean := true;
g_with_muxed_CS : boolean := false; g_with_muxed_CS : boolean := false;
g_with_watchdog : boolean := false; g_with_watchdog : boolean := false;
g_inj_per_EP : std_logic_vector(17 downto 0) := (others=>'0') g_inj_per_EP : std_logic_vector(17 downto 0) := (others=>'0');
g_phy_lpcalib : t_bool_array(0 to 17) := c_BOOL_FALSE_ARRAY
); );
port ( port (
sys_rst_n_i : in std_logic; -- global reset sys_rst_n_i : in std_logic; -- global reset
...@@ -282,7 +283,7 @@ architecture rtl of scb_top_bare is ...@@ -282,7 +283,7 @@ architecture rtl of scb_top_bare is
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
signal clk_sys : std_logic; signal clk_sys : std_logic;
signal clk_rx_vec : std_logic_vector(c_NUM_PORTS-1 downto 0); signal clk_rx_vec, clk_rx_sampled_vec : std_logic_vector(c_NUM_PORTS-1 downto 0);
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -336,6 +337,7 @@ architecture rtl of scb_top_bare is ...@@ -336,6 +337,7 @@ architecture rtl of scb_top_bare is
signal rst_periph_ref_n : std_logic; signal rst_periph_ref_n : std_logic;
signal rst_periph_dmtd_n : std_logic; signal rst_periph_dmtd_n : std_logic;
signal rst_periph_rxclk_n: std_logic_vector(c_NUM_PORTS-1 downto 0); signal rst_periph_rxclk_n: std_logic_vector(c_NUM_PORTS-1 downto 0);
signal rst_periph_txclk_n: std_logic_vector(c_NUM_PORTS-1 downto 0);
signal rst_ref_n : std_logic; signal rst_ref_n : std_logic;
signal rst_ext_n : std_logic; signal rst_ext_n : std_logic;
signal rst_dmtd_n : std_logic; signal rst_dmtd_n : std_logic;
...@@ -574,6 +576,15 @@ begin ...@@ -574,6 +576,15 @@ begin
synced_o => rst_periph_dmtd_n); synced_o => rst_periph_dmtd_n);
gen_rst_periph_rxclk : for i in 0 to c_NUM_PORTS-1 generate gen_rst_periph_rxclk : for i in 0 to c_NUM_PORTS-1 generate
U_sync_reset_txclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phys_i(i).ref_clk,
rst_n_i => '1',
data_i => rst_n_periph,
synced_o => rst_periph_txclk_n(i));
U_sync_reset_rxclk: gc_sync_ffs U_sync_reset_rxclk: gc_sync_ffs
generic map ( generic map (
g_sync_edge => "positive") g_sync_edge => "positive")
...@@ -603,12 +614,14 @@ begin ...@@ -603,12 +614,14 @@ begin
generic map ( generic map (
g_num_rx_clocks => c_NUM_PORTS, g_num_rx_clocks => c_NUM_PORTS,
g_num_ext_clks => 2, g_num_ext_clks => 2,
g_simulation => g_simulation) g_simulation => g_simulation,
g_phy_lpcalib => g_phy_lpcalib)
port map ( port map (
clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys, clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd_i, clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec, clk_rx_i => clk_rx_vec,
clk_rx_sampled_i => clk_rx_sampled_vec,
clk_ext_i => pll_status_i, -- FIXME: UGLY HACK clk_ext_i => pll_status_i, -- FIXME: UGLY HACK
clk_ext_mul_i => clk_ext_mul_i, clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i, clk_ext_mul_locked_i => clk_ext_mul_locked_i,
...@@ -781,7 +794,8 @@ begin ...@@ -781,7 +794,8 @@ begin
g_use_new_rxcrc => true, g_use_new_rxcrc => true,
g_use_new_txcrc => false, g_use_new_txcrc => false,
g_with_stop_traffic => g_with_watchdog, g_with_stop_traffic => g_with_watchdog,
g_ep_idx => i) g_phy_lpcalib => g_phy_lpcalib(i),
g_ep_idx => i)
port map ( port map (
clk_ref_i => clk_ref_i, clk_ref_i => clk_ref_i,
clk_sys_i => clk_sys, clk_sys_i => clk_sys,
...@@ -790,7 +804,7 @@ begin ...@@ -790,7 +804,7 @@ begin
rst_sys_n_i => rst_n_periph, rst_sys_n_i => rst_n_periph,
rst_ref_n_i => rst_periph_ref_n, rst_ref_n_i => rst_periph_ref_n,
rst_dmtd_n_i => rst_periph_dmtd_n, rst_dmtd_n_i => rst_periph_dmtd_n,
rst_txclk_n_i => rst_periph_ref_n, rst_txclk_n_i => rst_periph_txclk_n(i),
rst_rxclk_n_i => rst_periph_rxclk_n(i), rst_rxclk_n_i => rst_periph_rxclk_n(i),
pps_csync_p1_i => pps_csync, pps_csync_p1_i => pps_csync,
...@@ -798,6 +812,8 @@ begin ...@@ -798,6 +812,8 @@ begin
phy_rst_o => phys_o(i).rst, phy_rst_o => phys_o(i).rst,
phy_loopen_o => phys_o(i).loopen, phy_loopen_o => phys_o(i).loopen,
phy_lpc_stat_i => phys_i(i).lpc_stat,
phy_lpc_ctrl_o => phys_o(i).lpc_ctrl,
phy_rdy_i => phys_i(i).rdy, phy_rdy_i => phys_i(i).rdy,
phy_ref_clk_i => phys_i(i).ref_clk, phy_ref_clk_i => phys_i(i).ref_clk,
phy_tx_data_o => ep_dbg_data_array(i), -- phys_o(i).tx_data, -- phy_tx_data_o => ep_dbg_data_array(i), -- phys_o(i).tx_data, --
...@@ -877,6 +893,7 @@ begin ...@@ -877,6 +893,7 @@ begin
--------------------------- ---------------------------
clk_rx_vec(i) <= phys_i(i).rx_clk; clk_rx_vec(i) <= phys_i(i).rx_clk;
clk_rx_sampled_vec(i) <= phys_i(i).rx_sampled_clk;
end generate gen_endpoints_and_phys; end generate gen_endpoints_and_phys;
......
top/bare_top/wrsw_components_pkg.vhd
View file @ 5d5f1a74
...@@ -118,7 +118,8 @@ package wrsw_components_pkg is ...@@ -118,7 +118,8 @@ package wrsw_components_pkg is
component wr_gtx_phy_virtex6 component wr_gtx_phy_virtex6
generic ( generic (
g_simulation : integer; g_simulation : integer;
g_use_slave_tx_clock : integer); g_use_slave_tx_clock : integer;
g_rxclk_bufr : boolean);
port ( port (
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
tx_clk_i : in std_logic; tx_clk_i : in std_logic;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 5d5f1a74
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk -- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2012-02-21 -- Created : 2012-02-21
-- Last update: 2014-02-14 -- Last update: 2018-11-07
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -51,6 +51,8 @@ package wrsw_top_pkg is ...@@ -51,6 +51,8 @@ package wrsw_top_pkg is
syncen : std_logic; syncen : std_logic;
tx_data : std_logic_vector(15 downto 0); tx_data : std_logic_vector(15 downto 0);
tx_k : std_logic_vector(1 downto 0); tx_k : std_logic_vector(1 downto 0);
lpc_ctrl: std_logic_vector(15 downto 0);
end record; end record;
type t_phyif_input is record type t_phyif_input is record
...@@ -59,10 +61,12 @@ package wrsw_top_pkg is ...@@ -59,10 +61,12 @@ package wrsw_top_pkg is
tx_enc_err : std_logic; tx_enc_err : std_logic;
rx_data : std_logic_vector(15 downto 0); rx_data : std_logic_vector(15 downto 0);
rx_clk : std_logic; rx_clk : std_logic;
rx_sampled_clk : std_logic;
rx_k : std_logic_vector(1 downto 0); rx_k : std_logic_vector(1 downto 0);
rx_enc_err : std_logic; rx_enc_err : std_logic;
rx_bitslide : std_logic_vector(4 downto 0); rx_bitslide : std_logic_vector(4 downto 0);
rdy : std_logic; rdy : std_logic;
lpc_stat : std_logic_vector(15 downto 0);
end record; end record;
type t_phyif_output_array is array(integer range <>) of t_phyif_output; type t_phyif_output_array is array(integer range <>) of t_phyif_output;
...@@ -141,6 +145,40 @@ package wrsw_top_pkg is ...@@ -141,6 +145,40 @@ package wrsw_top_pkg is
rdy_o : out std_logic); rdy_o : out std_logic);
end component; end component;
component wr_gtx_phy_virtex6_lp
generic (
g_simulation : integer;
g_use_slave_tx_clock : integer;
g_rxclk_bufr : boolean := false;
g_txclk_bufr : boolean := false;
g_id : integer);
port (
clk_ref_i : in std_logic;
clk_gtx_i : in std_logic;
clk_dmtd_i : in std_logic;
tx_data_i : in std_logic_vector(15 downto 0);
tx_k_i : in std_logic_vector(1 downto 0);
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_rbclk_sampled_o : out std_logic;
rx_data_o : out std_logic_vector(15 downto 0);
rx_k_o : out std_logic_vector(1 downto 0);
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(4 downto 0);
rst_i : in std_logic;
loopen_i : in std_logic;
debug_i : in std_logic_vector(15 downto 0);
debug_o : out std_logic_vector(15 downto 0);
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic
);
end component;
component xwr_pps_gen component xwr_pps_gen
generic ( generic (
g_interface_mode : t_wishbone_interface_mode; g_interface_mode : t_wishbone_interface_mode;
...@@ -208,12 +246,15 @@ package wrsw_top_pkg is ...@@ -208,12 +246,15 @@ package wrsw_top_pkg is
generic ( generic (
g_num_rx_clocks : integer; g_num_rx_clocks : integer;
g_num_ext_clks : integer; g_num_ext_clks : integer;
g_simulation : boolean); g_simulation : boolean;
g_phy_lpcalib : t_bool_array(0 to 17));
port ( port (
clk_ref_i : in std_logic; clk_ref_i : in std_logic;
clk_sys_i : in std_logic; clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic; clk_dmtd_i : in std_logic;
clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0); clk_rx_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_rx_sampled_i : in std_logic_vector(g_num_rx_clocks-1 downto 0);
clk_ext_i : in std_logic; clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0); clk_ext_mul_i : in std_logic_vector(g_num_ext_clks-1 downto 0);
clk_ext_mul_locked_i: in std_logic; clk_ext_mul_locked_i: in std_logic;
...@@ -299,7 +340,8 @@ package wrsw_top_pkg is ...@@ -299,7 +340,8 @@ package wrsw_top_pkg is
g_with_PSTATS : boolean := true; g_with_PSTATS : boolean := true;
g_with_muxed_CS : boolean := false; g_with_muxed_CS : boolean := false;
g_with_watchdog : boolean := false; g_with_watchdog : boolean := false;
g_inj_per_EP : std_logic_vector(17 downto 0) := (others=>'0')); g_inj_per_EP : std_logic_vector(17 downto 0) := (others=>'0');
g_phy_lpcalib : t_bool_array(0 to 17) := c_BOOL_FALSE_ARRAY);
port ( port (
sys_rst_n_i : in std_logic; sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic; clk_startup_i : in std_logic;
...@@ -428,7 +470,8 @@ package wrsw_top_pkg is ...@@ -428,7 +470,8 @@ package wrsw_top_pkg is
rtu2tru_o : out t_rtu2tru; rtu2tru_o : out t_rtu2tru;
tru_enabled_i: in std_logic; tru_enabled_i: in std_logic;
wb_i : in t_wishbone_slave_in; wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out); wb_o : out t_wishbone_slave_out;
int_o : out std_logic);
end component; end component;
component xwrsw_rtu_new component xwrsw_rtu_new
generic ( generic (
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ 5d5f1a74
...@@ -346,24 +346,24 @@ NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i"; ...@@ -346,24 +346,24 @@ NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i";
TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %; TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19 #Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
NET "from_phys[0]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[1]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[2]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[3]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[4]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[5]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[6]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[7]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[8]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[8].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[9]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[9].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[10]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[10].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[11]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[11].gen_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[12]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[12].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[13]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[13].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[14]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[14].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[15]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[15].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[16]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[16].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "from_phys[17]_rx_clk" TNM="phy_rx_clocks"; NET "gen_phys[17].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM="phy_rx_clocks";
NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i; NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i;
...@@ -389,14 +389,14 @@ NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i; ...@@ -389,14 +389,14 @@ NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%; TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF # Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" LOC = SLICE_X1Y22; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" LOC = SLICE_X1Y22; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d1" LOC = SLICE_X1Y22;
#CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24; #CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24;
#CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24; #CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24;
#CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21; #CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21;
#CONFIG PROHIBIT = SLICE_X0Y22; #CONFIG PROHIBIT = SLICE_X0Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2"; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2"; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24; AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9; AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4; AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
...@@ -690,54 +690,37 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DM ...@@ -690,54 +690,37 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/U_sync_tag_strobe/sync0" TNM = Ignore_sync_ffs;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/clk_i_d3" TNM = Ignore_DMTD;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/06/18
INST "gen_phys[0].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[0].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[1].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[1].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[2].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[2].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[3].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[3].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[4].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[4].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[5].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[5].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[6].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[6].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[7].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[7].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[8].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[8].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[9].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[9].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[10].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[10].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[11].gen_lp.U_PHY/U_Sampler_RX/clk_i_d3" TNM = Ignore_DMTD;
INST "gen_phys[11].gen_lp.U_PHY/U_Sampler_TX/clk_i_d3" TNM = Ignore_DMTD;
TIMESPEC TS_ignore1 = FROM Ignore_DMTD TIG; TIMESPEC TS_ignore1 = FROM Ignore_DMTD TIG;
TIMESPEC TS_ignore2 = TO Ignore_DMTD TIG; TIMESPEC TS_ignore2 = TO Ignore_DMTD TIG;
TIMESPEC TS_ignore3 = FROM Ignore_sync_ffs TIG; TIMESPEC TS_ignore3 = FROM Ignore_sync_ffs TIG;
TIMESPEC TS_ignore4 = TO Ignore_sync_ffs TIG; TIMESPEC TS_ignore4 = TO Ignore_sync_ffs TIG;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25 #Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/04/25
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_0" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_1" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_2" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_3" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_4" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_5" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_6" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_7" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_8" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_9" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_10" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_11" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_12" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_13" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_14" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_15" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_16" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_17" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_18" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_19" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_20" TNM = DMTD_TAG_INT;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_int_21" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_1" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_int_2" TNM = DMTD_TAG_INT;
...@@ -1067,6 +1050,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DM ...@@ -1067,6 +1050,7 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_18" TNM = DMTD_TAG_INT; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_18" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_19" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_int_21" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/tag_int_0" TNM = DMTD_TAG_INT;
...@@ -1139,29 +1123,6 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DM ...@@ -1139,29 +1123,6 @@ INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DM
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_int_20" TNM = DMTD_TAG_INT;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/tag_o_21" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_0" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_1" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_2" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_3" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_4" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_5" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_6" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_7" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_8" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_9" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_10" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_11" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_12" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_13" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_14" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_15" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_16" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_17" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_18" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_19" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_20" TNM = DMTD_TAG_O;
#INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/tag_o_21" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_0" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_1" TNM = DMTD_TAG_O;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/tag_o_2" TNM = DMTD_TAG_O;
...@@ -1505,68 +1466,72 @@ TIMESPEC TS_ignore42 = FROM "fpga_clk_ref_p_i" TO "clk_sys" 20ns DATAPATHONLY; ...@@ -1505,68 +1466,72 @@ TIMESPEC TS_ignore42 = FROM "fpga_clk_ref_p_i" TO "clk_sys" 20ns DATAPATHONLY;
TIMESPEC TS_ignore43 = FROM "clk_sys" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY; TIMESPEC TS_ignore43 = FROM "clk_sys" TO "fpga_clk_ref_p_i" 20ns DATAPATHONLY;
TIMESPEC TS_ignore44 = FROM "clk_sys" TO "phy_rx_clocks" 20ns DATAPATHONLY; TIMESPEC TS_ignore44 = FROM "clk_sys" TO "phy_rx_clocks" 20ns DATAPATHONLY;
TIMESPEC TS_ignore45 = FROM "phy_rx_clocks" TO "clk_sys" 20ns DATAPATHONLY; TIMESPEC TS_ignore45 = FROM "phy_rx_clocks" TO "clk_sys" 20ns DATAPATHONLY;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/07/16
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[17].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[1].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[2].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[3].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[4].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[5].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[6].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[7].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[8].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[9].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[10].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[11].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[12].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[13].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[14].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[15].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#NET "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ref_dmtds[16].DMTD_REF/clk_in" TNM_NET = DMTD_div_clks;
#TIMESPEC TS_dmtd_input = FROM "DMTD_div_clks" TO "FFS" 0.5 ns DATAPATHONLY; #TIMESPEC TS_dmtd_input = FROM "DMTD_div_clks" TO "FFS" 0.5 ns DATAPATHONLY;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2013/11/06 #Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2013/11/06
NET "gen_phys_bufr[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys_bufr[0].U_PHY/rx_rec_clk_bufin; NET "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
NET "gen_phys_bufr[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys_bufr[1].U_PHY/rx_rec_clk_bufin; NET "gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].U_PHY/rx_rec_clk_bufin;
NET "gen_phys_bufr[2].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys_bufr[2].U_PHY/rx_rec_clk_bufin; NET "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].U_PHY/rx_rec_clk_bufin;
NET "gen_phys_bufr[3].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys_bufr[3].U_PHY/rx_rec_clk_bufin; NET "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[4].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin; NET "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[5].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].U_PHY/rx_rec_clk_bufin; NET "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[6].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[6].U_PHY/rx_rec_clk_bufin; NET "gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[6].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[7].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[7].U_PHY/rx_rec_clk_bufin; NET "gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[7].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[8].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[8].U_PHY/rx_rec_clk_bufin; NET "gen_phys[8].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[8].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[9].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[9].U_PHY/rx_rec_clk_bufin; NET "gen_phys[9].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[9].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[10].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[10].U_PHY/rx_rec_clk_bufin; NET "gen_phys[10].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[10].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[11].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[11].U_PHY/rx_rec_clk_bufin; NET "gen_phys[11].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[11].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[12].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[12].U_PHY/rx_rec_clk_bufin; NET "gen_phys[12].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[12].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[13].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[13].U_PHY/rx_rec_clk_bufin; NET "gen_phys[13].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[13].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[14].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[14].U_PHY/rx_rec_clk_bufin; NET "gen_phys[14].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[14].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[15].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[15].U_PHY/rx_rec_clk_bufin; NET "gen_phys[15].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[15].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[16].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[16].U_PHY/rx_rec_clk_bufin; NET "gen_phys[16].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[16].U_PHY/rx_rec_clk_bufin;
NET "gen_phys[17].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[17].U_PHY/rx_rec_clk_bufin; NET "gen_phys[17].gen_no_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[17].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_bufr_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys_bufr[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_bufr_1__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys_bufr[1].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_1__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_bufr_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys_bufr[2].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_bufr_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys_bufr[3].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_5__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_5__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_6__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_6__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[6].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_7__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_7__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[7].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_9__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[9].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_9__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[9].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_10__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[10].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_10__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[10].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_11__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[11].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_11__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[11].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_12__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[12].gen_no_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_12__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[12].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_13__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[13].gen_no_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_13__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[13].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_14__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[14].gen_no_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_14__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[14].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_15__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[15].gen_no_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_15__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[15].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_16__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[16].gen_no_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_16__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[16].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%; TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].gen_no_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17 #Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY; TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY; TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/07/04
NET "gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_0__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[1].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[1].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_1__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[1].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[2].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[2].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_2__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[2].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[3].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[3].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_3__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[3].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_4__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_5__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_6__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_7__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[8].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[8].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_8__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[8].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[9].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[9].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_9__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[9].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[10].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[10].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_10__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[10].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[11].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[11].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_11__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[11].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
top/scb_18ports/scb_top_synthesis.vhd
View file @ 5d5f1a74
...@@ -44,6 +44,7 @@ use work.wr_fabric_pkg.all; ...@@ -44,6 +44,7 @@ use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all; use work.endpoint_pkg.all;
use work.wr_txtsu_pkg.all; use work.wr_txtsu_pkg.all;
use work.wrsw_top_pkg.all; use work.wrsw_top_pkg.all;
use work.wrsw_shared_types_pkg.all;
library UNISIM; library UNISIM;
...@@ -345,7 +346,8 @@ architecture Behavioral of scb_top_synthesis is ...@@ -345,7 +346,8 @@ architecture Behavioral of scb_top_synthesis is
g_with_PSTATS : boolean; g_with_PSTATS : boolean;
g_with_muxed_CS : boolean; g_with_muxed_CS : boolean;
g_with_watchdog : boolean; g_with_watchdog : boolean;
g_inj_per_EP : std_logic_vector(17 downto 0)); g_inj_per_EP : std_logic_vector(17 downto 0);
g_phy_lpcalib : t_bool_array(0 to 17) := c_BOOL_FALSE_ARRAY);
port ( port (
sys_rst_n_i : in std_logic; sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic; clk_startup_i : in std_logic;
...@@ -437,6 +439,57 @@ architecture Behavioral of scb_top_synthesis is ...@@ -437,6 +439,57 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG1 : std_logic_vector(31 downto 0); signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0); signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0); signal TRIG3 : std_logic_vector(31 downto 0);
type t_phy_conf is record
rxclk_bufr : boolean;
txclk_bufr : boolean;
end record;
type t_phy_conf_array is array(integer range <>) of t_phy_conf;
constant c_PHY_CONF : t_phy_conf_array(0 to 17) :=
( -- rx_bufr, tx_bufr
0 => (false , true ),
1 => (false , true ),
2 => (false , true ),
3 => (false , true ),
4 => (false , false ),
5 => (false , false ),
6 => (false , false ),
7 => (false , false ),
8 => (false , true ),
9 => (false , true ),
10 => (false , true ),
11 => (false , true ),
12 => (false , false ),
13 => (false , false ),
14 => (false , false ),
15 => (false , false ),
16 => (true , false ),
17 => (true , false )
);
constant c_PHY_LPCALIB : t_bool_array(0 to 17) :=
(
0 => true,
1 => true,
2 => true,
3 => true,
4 => true,
5 => true,
6 => true,
7 => true,
8 => true,
9 => true,
10 => true,
11 => true,
12 => false,
13 => false,
14 => false,
15 => false,
16 => false,
17 => false
);
begin begin
--chipscope_icon_1 : chipscope_icon --chipscope_icon_1 : chipscope_icon
...@@ -713,65 +766,72 @@ begin ...@@ -713,65 +766,72 @@ begin
clk_gtx(13 downto 10) <= (others => clk_gtx4_7); clk_gtx(13 downto 10) <= (others => clk_gtx4_7);
clk_gtx(17 downto 14) <= (others => clk_gtx0_3); clk_gtx(17 downto 14) <= (others => clk_gtx0_3);
--generate first 4 GTXes with BUFR to reduce the number of global clocks gen_phys : for i in 0 to c_NUM_PHYS-1 generate
gen_phys_bufr : for i in 0 to 3 generate
-- Instantiate GTX with low phase drift calibration
U_PHY : wr_gtx_phy_virtex6 gen_lp: if c_PHY_LPCALIB(i) generate
generic map ( U_PHY : entity work.wr_gtx_phy_virtex6_lp
g_simulation => f_bool2int(g_simulation), generic map (
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4), g_simulation => f_bool2int(g_simulation),
g_use_bufr => true) g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr,
port map ( g_txclk_bufr => c_PHY_CONF(i).txclk_bufr,
clk_gtx_i => clk_gtx(i), g_id => i)
clk_ref_i => clk_ref, port map (
clk_gtx_i => clk_gtx(i),
tx_data_i => to_phys(i).tx_data, clk_ref_i => clk_ref,
tx_k_i => to_phys(i).tx_k, clk_dmtd_i => clk_dmtd,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err, tx_data_i => to_phys(i).tx_data,
rx_rbclk_o => from_phys(i).rx_clk, tx_k_i => to_phys(i).tx_k,
rx_data_o => from_phys(i).rx_data, tx_disparity_o => from_phys(i).tx_disparity,
rx_k_o => from_phys(i).rx_k, tx_enc_err_o => from_phys(i).tx_enc_err,
rx_enc_err_o => from_phys(i).rx_enc_err, rx_rbclk_o => from_phys(i).rx_clk,
rx_bitslide_o => from_phys(i).rx_bitslide, clk_sampled_o => from_phys(i).rx_sampled_clk,
rst_i => to_phys(i).rst, rx_data_o => from_phys(i).rx_data,
loopen_i => to_phys(i).loopen, rx_k_o => from_phys(i).rx_k,
pad_txn_o => gtx_txn_o(i), rx_enc_err_o => from_phys(i).rx_enc_err,
pad_txp_o => gtx_txp_o(i), rx_bitslide_o => from_phys(i).rx_bitslide,
pad_rxn_i => gtx_rxn_i(i), rst_i => to_phys(i).rst,
pad_rxp_i => gtx_rxp_i(i), lpc_stat_o => from_phys(i).lpc_stat,
rdy_o => from_phys(i).rdy); lpc_ctrl_i => to_phys(i).lpc_ctrl,
loopen_i => to_phys(i).loopen,
from_phys(i).ref_clk <= clk_ref; pad_txn_o => gtx_txn_o(i),
end generate gen_phys_bufr; pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
gen_phys : for i in 4 to c_NUM_PHYS-1 generate pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
U_PHY : wr_gtx_phy_virtex6 end generate gen_lp;
generic map (
g_simulation => f_bool2int(g_simulation), -- Instantiate regular GTX for all other ports
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4), gen_no_lp: if not c_PHY_LPCALIB(i) generate
g_use_bufr => false) U_PHY : entity work.wr_gtx_phy_virtex6
port map ( generic map (
clk_gtx_i => clk_gtx(i), g_simulation => f_bool2int(g_simulation),
clk_ref_i => clk_ref, g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr)
port map (
tx_data_i => to_phys(i).tx_data, clk_gtx_i => clk_gtx(i),
tx_k_i => to_phys(i).tx_k, clk_ref_i => clk_ref,
tx_disparity_o => from_phys(i).tx_disparity,
tx_enc_err_o => from_phys(i).tx_enc_err, tx_data_i => to_phys(i).tx_data,
rx_rbclk_o => from_phys(i).rx_clk, tx_k_i => to_phys(i).tx_k,
rx_data_o => from_phys(i).rx_data, tx_disparity_o => from_phys(i).tx_disparity,
rx_k_o => from_phys(i).rx_k, tx_enc_err_o => from_phys(i).tx_enc_err,
rx_enc_err_o => from_phys(i).rx_enc_err, rx_rbclk_o => from_phys(i).rx_clk,
rx_bitslide_o => from_phys(i).rx_bitslide, rx_data_o => from_phys(i).rx_data,
rst_i => to_phys(i).rst, rx_k_o => from_phys(i).rx_k,
loopen_i => to_phys(i).loopen, rx_enc_err_o => from_phys(i).rx_enc_err,
pad_txn_o => gtx_txn_o(i), rx_bitslide_o => from_phys(i).rx_bitslide,
pad_txp_o => gtx_txp_o(i), rst_i => to_phys(i).rst,
pad_rxn_i => gtx_rxn_i(i), loopen_i => to_phys(i).loopen,
pad_rxp_i => gtx_rxp_i(i), pad_txn_o => gtx_txn_o(i),
rdy_o => from_phys(i).rdy); pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
from_phys(i).rx_sampled_clk <= '0';
from_phys(i).lpc_stat <= (others => '0');
end generate gen_no_lp;
from_phys(i).ref_clk <= clk_ref; from_phys(i).ref_clk <= clk_ref;
end generate gen_phys; end generate gen_phys;
...@@ -801,7 +861,8 @@ begin ...@@ -801,7 +861,8 @@ begin
g_with_PSTATS => true, g_with_PSTATS => true,
g_with_muxed_CS => false, g_with_muxed_CS => false,
g_with_watchdog => true, g_with_watchdog => true,
g_inj_per_EP => "00" & x"0000") g_inj_per_EP => "00" & x"0000",
g_phy_lpcalib => c_PHY_LPCALIB)
port map ( port map (
sys_rst_n_i => sys_rst_n_i, sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup, clk_startup_i => clk_sys_startup,
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ 5d5f1a74
...@@ -47,6 +47,7 @@ NET "ljd_pll_locked_i" LOC = AH33; ...@@ -47,6 +47,7 @@ NET "ljd_pll_locked_i" LOC = AH33;
#NET "spll_dbg_o<3>" LOC=AM32; #NET "spll_dbg_o<3>" LOC=AM32;
#NET "spll_dbg_o<4>" LOC=AN32; #NET "spll_dbg_o<4>" LOC=AN32;
#NET "spll_dbg_o<5>" LOC=AP33; #NET "spll_dbg_o<5>" LOC=AP33;
#EBI BUS #EBI BUS
#NET "cpu_clk_i" LOC=""; #NET "cpu_clk_i" LOC="";
NET "cpu_cs_n_i" LOC="H34"; NET "cpu_cs_n_i" LOC="H34";
...@@ -157,10 +158,13 @@ NET "clk_sel_o" LOC="AK17"; ...@@ -157,10 +158,13 @@ NET "clk_sel_o" LOC="AK17";
#NET "gtx0_3_clk_p_i" LOC="AK6"; #NET "gtx0_3_clk_p_i" LOC="AK6";
#NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25"; #NET "gtx0_3_clk_n_i" IOSTANDARD="LVPECL_25";
#NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25"; #NET "gtx0_3_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx4_7_clk_n_i" LOC="AD5"; #NET "gtx4_7_clk_n_i" LOC="AD5";
#NET "gtx4_7_clk_p_i" LOC="AD6"; #NET "gtx4_7_clk_p_i" LOC="AD6";
#NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25"; #NET "gtx4_7_clk_n_i" IOSTANDARD="LVPECL_25";
#NET "gtx4_7_clk_p_i" IOSTANDARD="LVPECL_25"; #NET "gtx4_7_clk_p_i" IOSTANDARD="LVPECL_25";
NET "gtx8_11_clk_n_i" LOC="V5"; NET "gtx8_11_clk_n_i" LOC="V5";
NET "gtx8_11_clk_p_i" LOC="V6"; NET "gtx8_11_clk_p_i" LOC="V6";
...@@ -184,42 +188,61 @@ NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25"; ...@@ -184,42 +188,61 @@ NET "gtx16_19_clk_p_i" IOSTANDARD="LVPECL_25";
#NET "gtx_rxn_i[0]" LOC="AP6"; #NET "gtx_rxn_i[0]" LOC="AP6";
#NET "gtx_txp_o[0]" LOC="AP1"; #NET "gtx_txp_o[0]" LOC="AP1";
#NET "gtx_txn_o[0]" LOC="AP2"; #NET "gtx_txn_o[0]" LOC="AP2";
#NET "gtx_rxp_i[1]" LOC="AM5"; # gtx1 #NET "gtx_rxp_i[1]" LOC="AM5"; # gtx1
#NET "gtx_rxn_i[1]" LOC="AM6"; #NET "gtx_rxn_i[1]" LOC="AM6";
#NET "gtx_txp_o[1]" LOC="AN3"; #NET "gtx_txp_o[1]" LOC="AN3";
#NET "gtx_txn_o[1]" LOC="AN4"; #NET "gtx_txn_o[1]" LOC="AN4";
#NET "gtx_rxp_i[2]" LOC="AL3"; # gtx2 #NET "gtx_rxp_i[2]" LOC="AL3"; # gtx2
#NET "gtx_rxn_i[2]" LOC="AL4"; #NET "gtx_rxn_i[2]" LOC="AL4";
#NET "gtx_txp_o[2]" LOC="AM1"; #NET "gtx_txp_o[2]" LOC="AM1";
#NET "gtx_txn_o[2]" LOC="AM2"; #NET "gtx_txn_o[2]" LOC="AM2";
#NET "gtx_rxp_i[3]" LOC="AJ3"; #NET "gtx_rxp_i[3]" LOC="AJ3";
#NET "gtx_rxn_i[3]" LOC="AJ4"; #NET "gtx_rxn_i[3]" LOC="AJ4";
#NET "gtx_txp_o[3]" LOC="AK1"; #NET "gtx_txp_o[3]" LOC="AK1";
#NET "gtx_txn_o[3]" LOC="AK2"; #NET "gtx_txn_o[3]" LOC="AK2";
#NET "gtx_rxp_i[4]" LOC="AG3"; #NET "gtx_rxp_i[4]" LOC="AG3";
#NET "gtx_rxn_i[4]" LOC="AG4"; #NET "gtx_rxn_i[4]" LOC="AG4";
#NET "gtx_txp_o[4]" LOC="AH1"; #NET "gtx_txp_o[4]" LOC="AH1";
#NET "gtx_txn_o[4]" LOC="AH2"; #NET "gtx_txn_o[4]" LOC="AH2";
#NET "gtx_rxp_i[5]" LOC="AF5"; #NET "gtx_rxp_i[5]" LOC="AF5";
#NET "gtx_rxn_i[5]" LOC="AF6"; #NET "gtx_rxn_i[5]" LOC="AF6";
#NET "gtx_txp_o[5]" LOC="AF1"; #NET "gtx_txp_o[5]" LOC="AF1";
#NET "gtx_txn_o[5]" LOC="AF2"; #NET "gtx_txn_o[5]" LOC="AF2";
#NET "gtx_rxp_i[6]" LOC="AE3"; #NET "gtx_rxp_i[6]" LOC="AE3";
#NET "gtx_rxn_i[6]" LOC="AE4"; #NET "gtx_rxn_i[6]" LOC="AE4";
#NET "gtx_txp_o[6]" LOC="AD1"; #NET "gtx_txp_o[6]" LOC="AD1";
#NET "gtx_txn_o[6]" LOC="AD2"; #NET "gtx_txn_o[6]" LOC="AD2";
#NET "gtx_rxp_i[7]" LOC="AC3"; #NET "gtx_rxp_i[7]" LOC="AC3";
#NET "gtx_rxn_i[7]" LOC="AC4"; #NET "gtx_rxn_i[7]" LOC="AC4";
#NET "gtx_txp_o[7]" LOC="AB1"; #NET "gtx_txp_o[7]" LOC="AB1";
#NET "gtx_txn_o[7]" LOC="AB2"; #NET "gtx_txn_o[7]" LOC="AB2";
#NET "gtx_rxp_i[8]" LOC="AA3"; #NET "gtx_rxp_i[8]" LOC="AA3";
#NET "gtx_rxn_i[8]" LOC="AA4"; #NET "gtx_rxn_i[8]" LOC="AA4";
#NET "gtx_txp_o[8]" LOC="Y1"; #NET "gtx_txp_o[8]" LOC="Y1";
#NET "gtx_txn_o[8]" LOC="Y2"; #NET "gtx_txn_o[8]" LOC="Y2";
#NET "gtx_rxp_i[9]" LOC="W3"; #NET "gtx_rxp_i[9]" LOC="W3";
#NET "gtx_rxn_i[9]" LOC="W4"; #NET "gtx_rxn_i[9]" LOC="W4";
#NET "gtx_txp_o[9]" LOC="V1"; #NET "gtx_txp_o[9]" LOC="V1";
#NET "gtx_txn_o[9]" LOC="V2"; #NET "gtx_txn_o[9]" LOC="V2";
NET "gtx_rxp_i[7]" LOC="U3"; NET "gtx_rxp_i[7]" LOC="U3";
NET "gtx_rxn_i[7]" LOC="U4"; NET "gtx_rxn_i[7]" LOC="U4";
...@@ -316,49 +339,6 @@ TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %; ...@@ -316,49 +339,6 @@ TIMESPEC TS_ext_clk_10mhz_p_i = PERIOD "ext_clk_10mhz_p_i" 100 ns HIGH 50 %;
NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i"; NET "ext_clk_10mhz_n_i" TNM_NET = "ext_clk_10mhz_n_i";
TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %; TIMESPEC TS_ext_clk_10mhz_n_i = PERIOD "ext_clk_10mhz_n_i" 100 ns HIGH 50 %;
#Created by Constraints Editor (xc6vlx130t-ff1156-1) - 2012/03/19
#NET "gen_phys[0].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_0__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[1].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_1__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[1].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[2].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_2__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[3].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_3__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[4].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_4__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[4].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[4].U_PHY/tx_out_clk_bufin;
#TIMESPEC TS_gen_phys_4__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[4].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[5].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_5__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[6].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[6].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_6__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[6].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[7].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[7].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_7__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[7].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[8].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[8].U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_8__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[8].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[8].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[8].U_PHY/tx_out_clk_bufin;
#TIMESPEC TS_gen_phys_8__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[8].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[9].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[9].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_9__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[9].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[10].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[10].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_10__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[10].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[11].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[11].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_11__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[11].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[12].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[12].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_12__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[12].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[13].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[13].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_13__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[13].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[14].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[14].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_14__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[14].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[15].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[15].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_15__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[15].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[16].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[16].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_16__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[16].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[16].U_PHY/tx_out_clk_bufin" TNM_NET = gen_phys[16].U_PHY/tx_out_clk_bufin;
#TIMESPEC TS_gen_phys_16__U_PHY_tx_out_clk_bufin = PERIOD "gen_phys[16].U_PHY/tx_out_clk_bufin" 16 ns HIGH 50%;
#NET "gen_phys[17].U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[17].U_PHY/rx_rec_clk_bufin;
#TIMESPEC TS_gen_phys_17__U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[17].U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
#NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i; #NET "gtx0_3_clk_n_i" TNM_NET = gtx0_3_clk_n_i;
#TIMESPEC TS_gtx0_3_clk_n_i = PERIOD "gtx0_3_clk_n_i" 8 ns HIGH 50%; #TIMESPEC TS_gtx0_3_clk_n_i = PERIOD "gtx0_3_clk_n_i" 8 ns HIGH 50%;
#NET "gtx0_3_clk_p_i" TNM_NET = gtx0_3_clk_p_i; #NET "gtx0_3_clk_p_i" TNM_NET = gtx0_3_clk_p_i;
...@@ -381,14 +361,14 @@ NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i; ...@@ -381,14 +361,14 @@ NET "gtx16_19_clk_p_i" TNM_NET = gtx16_19_clk_p_i;
TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%; TIMESPEC TS_gtx16_19_clk_p_i = PERIOD "gtx16_19_clk_p_i" 8 ns HIGH 50%;
# Avoid noisy DFFs near DMTD demodulation DFF # Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" LOC = SLICE_X1Y22; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" LOC = SLICE_X1Y22; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d1" LOC = SLICE_X1Y22;
#CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24; #CONFIG PROHIBIT = SLICE_X2Y19:SLICE_X5Y24;
#CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24; #CONFIG PROHIBIT = SLICE_X0Y23:SLICE_X1Y24;
#CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21; #CONFIG PROHIBIT = SLICE_X0Y19:SLICE_X1Y21;
#CONFIG PROHIBIT = SLICE_X0Y22; #CONFIG PROHIBIT = SLICE_X0Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2"; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2"; INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_ext_dmtds[1].U_DMTD_EXT_internal/gen_builtin.U_Sampler/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24; AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9; AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4; AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
...@@ -398,3 +378,37 @@ AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED; ...@@ -398,3 +378,37 @@ AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17 #Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2014/02/17
TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY; TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_p_i" TO "U_swcore_pll_clkout0" 20 ns DATAPATHONLY;
TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY; TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_p_i" 20 ns DATAPATHONLY;
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2019/07/12
NET "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_0__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[0].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_0__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[0].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_1__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[1].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[1].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[1].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_1__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[1].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_2__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[2].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[2].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[2].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_2__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[2].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_3__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[3].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[3].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[3].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_3__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[3].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_4__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[4].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_4__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[4].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_5__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[5].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_5__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[5].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_6__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[6].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_6__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[6].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
NET "gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin" TNM_NET = gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin;
TIMESPEC TS_gen_phys_7__gen_lp_U_PHY_rx_rec_clk_bufin = PERIOD "gen_phys[7].gen_lp.U_PHY/rx_rec_clk_bufin" 16 ns HIGH 50%;
NET "gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf" TNM_NET = gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf;
TIMESPEC TS_gen_phys_7__gen_lp_U_PHY_tx_out_clk_buf = PERIOD "gen_phys[7].gen_lp.U_PHY/tx_out_clk_buf" 16 ns HIGH 50%;
top/scb_8ports/scb_top_synthesis.vhd
View file @ 5d5f1a74
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk -- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT -- Company : CERN BE-CO-HT
-- Created : 2012-03-07 -- Created : 2012-03-07
-- Last update: 2014-03-20 -- Last update: 2019-07-03
-- Platform : FPGA-generic -- Platform : FPGA-generic
-- Standard : VHDL -- Standard : VHDL
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
...@@ -44,7 +44,7 @@ use work.wr_fabric_pkg.all; ...@@ -44,7 +44,7 @@ use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all; use work.endpoint_pkg.all;
use work.wr_txtsu_pkg.all; use work.wr_txtsu_pkg.all;
use work.wrsw_top_pkg.all; use work.wrsw_top_pkg.all;
use work.wrsw_shared_types_pkg.all;
library UNISIM; library UNISIM;
use UNISIM.vcomponents.all; use UNISIM.vcomponents.all;
...@@ -345,7 +345,8 @@ architecture Behavioral of scb_top_synthesis is ...@@ -345,7 +345,8 @@ architecture Behavioral of scb_top_synthesis is
g_with_PSTATS : boolean; g_with_PSTATS : boolean;
g_with_muxed_CS : boolean; g_with_muxed_CS : boolean;
g_with_watchdog : boolean; g_with_watchdog : boolean;
g_inj_per_EP : std_logic_vector(17 downto 0)); g_inj_per_EP : std_logic_vector(17 downto 0);
g_phy_lpcalib : t_bool_array(0 to 17) := c_BOOL_FALSE_ARRAY);
port ( port (
sys_rst_n_i : in std_logic; sys_rst_n_i : in std_logic;
clk_startup_i : in std_logic; clk_startup_i : in std_logic;
...@@ -437,51 +438,39 @@ architecture Behavioral of scb_top_synthesis is ...@@ -437,51 +438,39 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG1 : std_logic_vector(31 downto 0); signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0); signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0); signal TRIG3 : std_logic_vector(31 downto 0);
begin
--chipscope_icon_1 : chipscope_icon type t_phy_conf is record
-- port map ( rxclk_bufr : boolean;
-- CONTROL0 => CONTROL); txclk_bufr : boolean;
end record;
--chipscope_ila_1 : chipscope_ila type t_phy_conf_array is array(integer range <>) of t_phy_conf;
-- port map (
-- CONTROL => CONTROL, constant c_PHY_CONF : t_phy_conf_array(0 to 7) :=
-- CLK => clk_25mhz, ( -- rx_bufr, tx_bufr
-- TRIG0 => TRIG0, 0 => (false , true ),
-- TRIG1 => TRIG1, 1 => (false , true ),
-- TRIG2 => TRIG2, 2 => (false , true ),
-- TRIG3 => TRIG3); 3 => (false , true ),
4 => (false , false ),
--TRIG0(0) <= mbl_scl_b(0); 5 => (false , false ),
--TRIG0(1) <= mbl_sda_b(0); 6 => (false , false ),
--TRIG0(2) <= mbl_scl_b(1); 7 => (false , false )
--TRIG0(3) <= mbl_sda_b(1); );
--TRIG1 <= cpu_data_b;
--TRIG2(0) <= cpu_cs_n_i; constant c_PHY_LPCALIB : t_bool_array(0 to 17) :=
--TRIG2(1) <= cpu_rd_n_i; (
--TRIG2(2) <= cpu_wr_n_i; 0 => true,
--TRIG2(3) <= sys_rst_n_i; 1 => true,
2 => true,
3 => true,
--U_Clk_Buf_GTX0_3 : IBUFDS_GTXE1 4 => true,
-- port map 5 => true,
-- ( 6 => true,
-- O => clk_gtx0_3, 7 => true,
-- ODIV2 => open, others => false
-- CEB => '0', );
-- I => gtx0_3_clk_p_i,
-- IB => gtx0_3_clk_n_i begin
-- );
--U_Clk_Buf_GTX4_7 : IBUFDS_GTXE1
-- port map
-- (
-- O => clk_gtx4_7,
-- ODIV2 => open,
-- CEB => '0',
-- I => gtx4_7_clk_p_i,
-- IB => gtx4_7_clk_n_i
-- );
U_Clk_Buf_GTX8_11 : IBUFDS_GTXE1 U_Clk_Buf_GTX8_11 : IBUFDS_GTXE1
port map port map
...@@ -646,15 +635,15 @@ begin ...@@ -646,15 +635,15 @@ begin
clk_ext_mul_vec(1) <= ljd_clk_62mhz_bufr; clk_ext_mul_vec(1) <= ljd_clk_62mhz_bufr;
--dbg_clk_ext_o <= clk_ext_mul; --dbg_clk_ext_o <= clk_ext_mul;
local_reset <= not sys_rst_n_i; local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse U_Extend_EXT_Reset: gc_extend_pulse
generic map ( generic map (
g_width => 1000) g_width => 1000)
port map( port map(
clk_i => clk_sys, clk_i => clk_sys,
rst_n_i => sys_rst_n_i, rst_n_i => sys_rst_n_i,
pulse_i => local_reset, pulse_i => local_reset,
extended_o => ext_pll_reset); extended_o => ext_pll_reset);
------------------------------------------------ ------------------------------------------------
cmp_wb_cpu_bridge : wb_cpu_bridge cmp_wb_cpu_bridge : wb_cpu_bridge
...@@ -716,64 +705,70 @@ begin ...@@ -716,64 +705,70 @@ begin
--clk_gtx(14 downto 12) <= (others => clk_gtx12_15); --clk_gtx(14 downto 12) <= (others => clk_gtx12_15);
--clk_gtx(17 downto 16) <= (others => clk_gtx16_19); --clk_gtx(17 downto 16) <= (others => clk_gtx16_19);
--generate first 4 GTXes with BUFR to reduce the number of global clocks --generate first 4 GTXes with BUFR to reduce the number of global clocks
gen_phys_bufr : for i in 0 to 3 generate gen_phys : for i in 0 to c_NUM_PHYS-1 generate
U_PHY : wr_gtx_phy_virtex6 -- Instantiate GTX with low phase drift calibration
generic map ( gen_lp: if c_PHY_LPCALIB(i) generate
g_simulation => f_bool2int(g_simulation), U_PHY : entity work.wr_gtx_phy_virtex6_lp
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4), generic map (
g_use_bufr => true) g_simulation => f_bool2int(g_simulation),
port map ( g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr,
clk_gtx_i => clk_gtx(i), g_txclk_bufr => c_PHY_CONF(i).txclk_bufr,
clk_ref_i => clk_ref, g_id => i)
port map (
tx_data_i => to_phys(i).tx_data, clk_gtx_i => clk_gtx(i),
tx_k_i => to_phys(i).tx_k, clk_ref_i => clk_ref,
tx_disparity_o => from_phys(i).tx_disparity, clk_dmtd_i => clk_dmtd,
tx_enc_err_o => from_phys(i).tx_enc_err,
rx_rbclk_o => from_phys(i).rx_clk, tx_data_i => to_phys(i).tx_data,
rx_data_o => from_phys(i).rx_data, tx_k_i => to_phys(i).tx_k,
rx_k_o => from_phys(i).rx_k, tx_disparity_o => from_phys(i).tx_disparity,
rx_enc_err_o => from_phys(i).rx_enc_err, tx_enc_err_o => from_phys(i).tx_enc_err,
rx_bitslide_o => from_phys(i).rx_bitslide, rx_rbclk_o => from_phys(i).rx_clk,
rst_i => to_phys(i).rst, clk_sampled_o =>from_phys(i).rx_sampled_clk,
loopen_i => to_phys(i).loopen, rx_data_o => from_phys(i).rx_data,
pad_txn_o => gtx_txn_o(i), rx_k_o => from_phys(i).rx_k,
pad_txp_o => gtx_txp_o(i), rx_enc_err_o => from_phys(i).rx_enc_err,
pad_rxn_i => gtx_rxn_i(i), rx_bitslide_o => from_phys(i).rx_bitslide,
pad_rxp_i => gtx_rxp_i(i), rst_i => to_phys(i).rst,
rdy_o => from_phys(i).rdy); lpc_stat_o => from_phys(i).lpc_stat,
lpc_ctrl_i => to_phys(i).lpc_ctrl,
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys_bufr; loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
gen_phys : for i in 4 to c_NUM_PHYS-1 generate pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
U_PHY : wr_gtx_phy_virtex6 pad_rxp_i => gtx_rxp_i(i),
generic map ( rdy_o => from_phys(i).rdy);
g_simulation => f_bool2int(g_simulation), end generate gen_lp;
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr => false) -- Instantiate regular GTX for all other ports
port map ( gen_no_lp: if not c_PHY_LPCALIB(i) generate
clk_gtx_i => clk_gtx(i), U_PHY : entity work.wr_gtx_phy_virtex6
clk_ref_i => clk_ref, generic map (
g_simulation => f_bool2int(g_simulation),
tx_data_i => to_phys(i).tx_data, g_rxclk_bufr => c_PHY_CONF(i).rxclk_bufr)
tx_k_i => to_phys(i).tx_k, port map (
tx_disparity_o => from_phys(i).tx_disparity, clk_gtx_i => clk_gtx(i),
tx_enc_err_o => from_phys(i).tx_enc_err, clk_ref_i => clk_ref,
rx_rbclk_o => from_phys(i).rx_clk,
rx_data_o => from_phys(i).rx_data, tx_data_i => to_phys(i).tx_data,
rx_k_o => from_phys(i).rx_k, tx_k_i => to_phys(i).tx_k,
rx_enc_err_o => from_phys(i).rx_enc_err, tx_disparity_o => from_phys(i).tx_disparity,
rx_bitslide_o => from_phys(i).rx_bitslide, tx_enc_err_o => from_phys(i).tx_enc_err,
rst_i => to_phys(i).rst, rx_rbclk_o => from_phys(i).rx_clk,
loopen_i => to_phys(i).loopen, rx_data_o => from_phys(i).rx_data,
pad_txn_o => gtx_txn_o(i), rx_k_o => from_phys(i).rx_k,
pad_txp_o => gtx_txp_o(i), rx_enc_err_o => from_phys(i).rx_enc_err,
pad_rxn_i => gtx_rxn_i(i), rx_bitslide_o => from_phys(i).rx_bitslide,
pad_rxp_i => gtx_rxp_i(i), rst_i => to_phys(i).rst,
rdy_o => from_phys(i).rdy); loopen_i => to_phys(i).loopen,
pad_txn_o => gtx_txn_o(i),
pad_txp_o => gtx_txp_o(i),
pad_rxn_i => gtx_rxn_i(i),
pad_rxp_i => gtx_rxp_i(i),
rdy_o => from_phys(i).rdy);
end generate gen_no_lp;
from_phys(i).ref_clk <= clk_ref; from_phys(i).ref_clk <= clk_ref;
end generate gen_phys; end generate gen_phys;
...@@ -803,8 +798,8 @@ begin ...@@ -803,8 +798,8 @@ begin
g_with_PSTATS => true, g_with_PSTATS => true,
g_with_muxed_CS => false, g_with_muxed_CS => false,
g_with_watchdog => true, g_with_watchdog => true,
g_inj_per_EP => "00" & x"0000" g_inj_per_EP => "00" & x"0000",
) g_phy_lpcalib => c_PHY_LPCALIB)
port map ( port map (
sys_rst_n_i => sys_rst_n_i, sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup, clk_startup_i => clk_sys_startup,
......
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