Update .gitlab-ci.yml

5d0fd345 · Konstantinos Blantos · 7de968c6 · 5d0fd345
Commit 5d0fd345 authored Feb 10, 2022 by Konstantinos Blantos
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Showing with 26 additions and 5 deletions

.gitlab-ci.yml .gitlab-ci.yml +26 -5

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--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -39,10 +39,33 @@ stages:
 #     - hdlmake makefile
 #     - make

-job_scb_top_8p_syn:
+#job_scb_top_8p_syn:
+#    stage: syn
+#    tags:
+#     - xilinx_ISE_14.7 
+#    script:
+#     - /entrypoint.sh
+#     - source ~/setup_ise147.sh
+#     - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
+#     - cd top/bare_top
+#     - python gen_sdbsyn.py --project wr_switch
+#     - cat synthesis_descriptor.vhd
+#     - cd ../../syn/scb_8ports 
+#     - hdlmake makefile 
+#     - make
+#    artifacts:
+#     name: SCB_TOP_8P_CI_$CI_JOB_ID
+#     paths:
+#     - syn/scb_8ports/*.syr
+#     - syn/scb_8ports/*.mrp
+#     - syn/scb_8ports/*.bit
+#     - syn/scb_8ports/*.bin
+#     - syn/scb_8ports/*.par
+#     - syn/scb_8ports/*.twr
+
+job_scb_top_18p_syn:
    stage: syn
    tags:
-#     - ise_14.7
     - xilinx_ISE_14.7 
    script:
     - /entrypoint.sh
@@ -51,7 +74,7 @@ job_scb_top_8p_syn:
     - cd top/bare_top
     - python gen_sdbsyn.py --project wr_switch
     - cat synthesis_descriptor.vhd
-     - cd ../../syn/scb_8ports 
+     - cd ../../syn/scb_18ports 
     - hdlmake makefile 
     - make
    artifacts:
@@ -63,5 +86,3 @@ job_scb_top_8p_syn:
     - syn/scb_8ports/*.bin
     - syn/scb_8ports/*.par
     - syn/scb_8ports/*.twr
-
-