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White Rabbit Switch - Gateware
Commit 3d3a035a authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wrsw_swcore/mpm: faster RR arbiters, new patial select encoding scheme

parent 5cf8744e
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modules/wrsw_swcore/mpm/mpm_read_path.vhd
View file @ 3d3a035a
......@@ -10,17 +10,17 @@ use work.genram_pkg.all; -- for f_log2_size
entity mpm_read_path is
generic (
g_data_width : integer;
g_ratio : integer;
g_page_size : integer;
g_num_pages : integer;
g_num_ports : integer;
g_fifo_size : integer;
g_page_addr_width : integer;
g_partial_select_width : integer;
g_max_oob_size : integer;
g_max_packet_size : integer;
g_ll_data_width : integer
g_data_width : integer := 6;
g_ratio : integer := 6;
g_page_size : integer := 66;
g_num_pages : integer := 1024;
g_num_ports : integer := 19;
g_fifo_size : integer := 8;
g_page_addr_width : integer := 10;
g_partial_select_width : integer := 2;
g_max_oob_size : integer := 3;
g_max_packet_size : integer := 10000;
g_ll_data_width : integer := 15
);
port(
......@@ -216,19 +216,26 @@ begin -- rtl
end generate gen_serialize_ios;
-- The actual round-robin arbiter for muxing memory accesses.
p_mem_arbiter : process(clk_core_i)
begin
if rising_edge(clk_core_i) then
if rst_n_core_i = '0' then
mem_grant <= (others => '0');
else
f_rr_arbitrate(mem_req, mem_grant, mem_grant);
end if;
end if;
end process;
--p_mem_arbiter : process(clk_core_i)
--begin
-- if rising_edge(clk_core_i) then
-- if rst_n_core_i = '0' then
-- mem_grant <= (others => '0');
-- else
-- f_rr_arbitrate(mem_req, mem_grant, mem_grant);
-- end if;
-- end if;
--end process;
U_Mem_Arbiter: gc_rr_arbiter
generic map (
g_size => g_num_ports)
port map (
clk_i => clk_core_i,
rst_n_i => rst_n_core_i,
req_i => mem_req,
grant_o => mem_grant);
gen_mux_inputs : for i in 0 to g_num_ports-1 generate
rd_mux_a_in(c_fbm_addr_width * (i + 1) - 1 downto c_fbm_addr_width * i) <= core(i).fbm_addr;
......@@ -293,23 +300,30 @@ begin -- rtl
-- The arbiter for accessing the linked list
p_ll_arbiter : process(clk_io_i)
begin
if rising_edge(clk_io_i) then
if rst_n_io_i = '0' then
ll_grant <= (others => '0');
else
f_rr_arbitrate(ll_req, ll_grant, ll_grant);
end if;
end if;
end process;
--p_ll_arbiter : process(clk_io_i)
--begin
-- if rising_edge(clk_io_i) then
-- if rst_n_io_i = '0' then
-- ll_grant <= (others => '0');
-- else
-- f_rr_arbitrate(ll_req, ll_grant, ll_grant);
-- end if;
-- end if;
--end process;
gen_ll_access_arbiter : for i in 0 to g_num_ports-1 generate
ll_req(i) <= io(i).ll_req and not io(i).ll_grant;
ll_req(i) <= io(i).ll_req ; --and not io(i).ll_grant;
io(i).ll_grant <= ll_grant(i);
end generate gen_ll_access_arbiter;
U_LL_Arbiter: gc_rr_arbiter
generic map (
g_size => g_num_ports)
port map (
clk_i => clk_io_i,
rst_n_i => rst_n_io_i,
req_i => ll_req,
grant_o => ll_grant);
p_ll_mux_addr : process(clk_io_i)
variable muxed : std_logic_vector(g_page_addr_width-1 downto 0);
......
modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd
View file @ 3d3a035a
......@@ -110,8 +110,6 @@ architecture behavioral of mpm_rpath_io_block is
next_page : std_logic_vector(g_page_addr_width-1 downto 0);
dsel : std_logic_vector(g_partial_select_width-1 downto 0);
size : std_logic_vector(f_log2_size(g_page_size + 1)-1 downto 0);
oob_size : std_logic_vector(c_max_oob_size_width - 1 downto 0);
oob_dsel : std_logic_vector(g_partial_select_width - 1 downto 0);
end record;
......@@ -146,22 +144,15 @@ architecture behavioral of mpm_rpath_io_block is
-- next packet.
signal fetch_abort : std_logic;
signal fetch_dsel_words : unsigned(f_log2_size(g_page_size+1)-1 downto 0);
signal fetch_oob_dsel : std_logic_vector(g_partial_select_width-1 downto 0);
signal saved_dat_dsel : std_logic_vector(g_partial_select_width-1 downto 0);
signal saved_oob_dsel : std_logic_vector(g_partial_select_width-1 downto 0);
-- Datapath signals
signal df_we_d0 : std_logic;
signal last_page : std_logic;
signal words_total : unsigned(c_word_count_width-1 downto 0);
signal dsel_words_total : unsigned(c_word_count_width-1 downto 0);
signal words_xmitted : unsigned(c_word_count_width-1 downto 0);
signal last_int, d_valid_int, df_rd_int, d_endOfData_int : std_logic;
signal last_int, d_valid_int, df_rd_int : std_logic;
signal pf_we_int : std_logic;
signal ll_req_int, ll_grant_d0, ll_grant_d1 : std_logic;
......@@ -203,7 +194,6 @@ begin -- behavioral
--counters_equal <= '1' when (words_total = words_xmitted) else '0';
counters_equal <= '1' when (words_total = words_xmitted and rport_dreq_i = '1') else '0';
-- ML
data_dsel_valid <= '1' when (dsel_words_total = words_xmitted and rport_dreq_i = '1') else '0';
wait_next_valid_ll_read <= '1' when ((words_total < words_xmitted+2) and
last_int = '0' and
......@@ -217,33 +207,22 @@ begin -- behavioral
if rising_edge(clk_io_i) then
if rst_n_io_i = '0' or (last_int = '1' and d_valid_int = '1') then
words_total <= (others => '0');
dsel_words_total<= (others => '0');
words_xmitted <= to_unsigned(1, words_xmitted'length);
-- ML
-- last_int <= '0';
d_counter_equal <= '0';
d_endOfData_int <= '0';
else
if(data_dsel_valid = '1') then
saved_dat_dsel <= fetch_dsel;
elsif(fetch_last = '1' and fetch_ack = '1') then
saved_oob_dsel <= fetch_oob_dsel;
end if;
if(df_rd_int = '1') then
words_xmitted <= words_xmitted + 1;
end if;
if(fetch_ack = '1') then
--if(fetch_valid = '1') then
if(fetch_first = '1') then
words_total <= resize(fetch_pg_words, words_total'length);
dsel_words_total <= resize(fetch_dsel_words, dsel_words_total'length);
else
-- if(fetch_first = '1') then
-- words_total <= resize(fetch_pg_words, words_total'length);
-- else
words_total <= words_total + fetch_pg_words;
dsel_words_total <= dsel_words_total + fetch_dsel_words;
end if;
-- end if;
end if;
-- ML:
......@@ -251,7 +230,6 @@ begin -- behavioral
d_counter_equal <= counters_equal;
---------
d_endOfData_int <= data_dsel_valid;
end if;
end if;
end process;
......@@ -283,8 +261,7 @@ begin -- behavioral
rport_dlast_o <= last_int;
rport_d_o <= df_d_i;
rport_dsel_o <= saved_dat_dsel when d_endOfData_int = '1' else -- order is important
saved_oob_dsel when last_int = '1' else (others => '1'); -- first eod, then oob
rport_dsel_o <= (others => '1');
rport_pg_req_o <= rport_pg_req;
-------------------------------------------------------------------------------
-- Page fetcher logic
......@@ -298,15 +275,7 @@ begin -- behavioral
cur_ll.valid <= ll_data_i(g_ll_data_width-1);
-- 1: number of the words in page (1 = 1 word .. g_page_size-1 = full page)
cur_ll.size <= ll_data_i(c_page_size_width-1 downto 0);
-- 1: partial select bits (number of bytes in the last word of the page. For
-- 16-bit datapath: 0 = 1 byte, 1 = 2 bytes, etc.)
cur_ll.dsel <= ll_data_i(g_ll_data_width-3 downto g_ll_data_width-2-g_partial_select_width);
cur_ll.oob_size <= ll_data_i(g_ll_data_width-2-g_partial_select_width-1 downto
g_ll_data_width-2-g_partial_select_width-c_max_oob_size_width);
cur_ll.oob_dsel <= ll_data_i(g_page_addr_width-1 downto g_page_addr_width-g_partial_select_width);
fetch_valid <= fvalid_int and not fetch_ack;
p_count_down_start : process(clk_io_i)
......@@ -333,8 +302,6 @@ begin -- behavioral
ll_req_int <= '0';
ll_grant_d0 <= '0';
ll_grant_d1 <= '0';
fetch_dsel_words<= (others =>'0');
fetch_oob_dsel <= (others =>'0');
wait_first_fetched <='1';
fetch_first <= '0';
else
......@@ -380,21 +347,11 @@ begin -- behavioral
fetch_pg_words <= unsigned(cur_ll.size);
fetch_pg_lines <= f_fast_div_pagesize(unsigned(cur_ll.size), g_ratio);
fetch_pg_addr <= cur_page;
fetch_oob_dsel <= cur_ll.oob_dsel;
fvalid_int <= '1';
fetch_last <= '1';
fetch_dsel <= cur_ll.dsel;
fetch_dsel_words <= unsigned(cur_ll.size) - unsigned(cur_ll.oob_size);
else
page_state <= WAIT_ACK;
if(unsigned(cur_ll.oob_size) /= to_unsigned(0, c_max_oob_size_width)) then
fetch_dsel <= cur_ll.dsel;
fetch_dsel_words <= to_unsigned(g_page_size, fetch_dsel_words'length) - resize(unsigned(cur_ll.oob_size), fetch_dsel_words'length);
else
fetch_dsel_words <= to_unsigned(g_page_size, fetch_pg_words'length);
end if;
fetch_pg_words <= to_unsigned(g_page_size, fetch_pg_words'length);
fetch_pg_lines <= to_unsigned(c_lines_per_page, fetch_pg_lines'length);
fetch_pg_addr <= cur_page;
......
modules/wrsw_swcore/mpm/mpm_top.vhd
View file @ 3d3a035a
......@@ -198,14 +198,15 @@ begin -- rtl
U_F_B_Memory : generic_dpram
generic map (
g_data_width => g_data_width * g_ratio,
g_size => g_num_pages * (g_page_size / g_ratio))
g_size => g_num_pages * (g_page_size / g_ratio),
g_dual_clock => false)
port map (
rst_n_i => rst_n_core,
clka_i => clk_core_i,
wea_i => fbm_we,
aa_i => fbm_wr_addr,
da_i => fbm_wr_data,
clkb_i => clk_core_i,
clkb_i => '0',
web_i => '0',
ab_i => fbm_rd_addr,
qb_o => fbm_rd_data);
......
modules/wrsw_swcore/mpm/mpm_write_path.vhd
View file @ 3d3a035a
......@@ -51,12 +51,12 @@ use work.genram_pkg.all; -- for f_log2_size
entity mpm_write_path is
generic (
g_data_width : integer := 10;
g_ratio : integer := 4;
g_page_size : integer := 64;
g_data_width : integer := 8;
g_ratio : integer := 6;
g_page_size : integer := 66;
g_num_pages : integer := 2048;
g_num_ports : integer := 18;
g_fifo_size : integer := 4;
g_num_ports : integer := 19;
g_fifo_size : integer := 8;
g_page_addr_width : integer := 11;
g_partial_select_width : integer := 1
);
......@@ -142,6 +142,10 @@ architecture rtl of mpm_write_path is
signal fbm_we_d : std_logic_vector(2 downto 0);
signal wr_mux_sel : std_logic_vector(g_num_ports-1 downto 0);
begin -- rtl
......@@ -183,17 +187,27 @@ begin -- rtl
end process;
end generate gen_input_arbiter_ios;
-- The actual round-robin arbiter.
p_input_arbiter : process(clk_core_i)
begin
if rising_edge(clk_core_i) then
if rst_n_core_i = '0' then
arb_grant <= (others => '0');
else
f_rr_arbitrate(arb_req, arb_grant, arb_grant);
end if;
end if;
end process;
U_RR_Arbiter: gc_rr_arbiter
generic map (
g_size => g_num_ports)
port map (
clk_i => clk_core_i,
rst_n_i => rst_n_core_i,
req_i => arb_req,
grant_o => arb_grant);
-- -- The actual round-robin arbiter.
--p_input_arbiter : process(clk_core_i)
--begin
-- if rising_edge(clk_core_i) then
-- if rst_n_core_i = '0' then
-- arb_grant <= (others => '0');
-- else
-- f_rr_arbitrate(arb_req, arb_grant, arb_grant);
-- end if;
-- end if;
--end process;
......
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