add HWIU module for reporting gateware version to the SW

3b0aeb80 · Grzegorz Daniluk · e27e943f · 3b0aeb80 · 3b0aeb80 · 3b0aeb80
Commit 3b0aeb80 authored Jun 06, 2013 by Grzegorz Daniluk
10 changed files
--- a/Manifest.py
+++ b/Manifest.py
@@ -4,6 +4,7 @@ modules = { "local" : [
 				"modules/wrsw_txtsu",
 				"modules/wrsw_swcore",
 				"modules/wrsw_rtu",
+        "modules/wrsw_hwiu",
 				"platform/virtex6/chipscope",
 				"platform/xilinx"],
 				"git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git" ]

--- a/modules/wrsw_hwiu/Manifest.py
+++ b/modules/wrsw_hwiu/Manifest.py
+files = ["wrsw_hwiu.vhd", "hwiu_wishbone_slave.vhd", "hwiu_wbgen2_pkg.vhd", "xwrsw_hwiu.vhd", "hwinfo_pkg.vhd", "gw_ver_pkg.vhd"]
--- a/modules/wrsw_hwiu/gen_ver.py
+++ b/modules/wrsw_hwiu/gen_ver.py
+#!/usr/bin/python
+
+import sys
+import subprocess
+import datetime
+
+c_PKG_FILE    = "/modules/wrsw_hwiu/gw_ver_pkg.vhd"
+c_PKG_LIB     = "library ieee;\nuse ieee.std_logic_1164.all;\n"
+c_PKG_HEAD    = "--generated automatically by gen_ver.py script--\npackage hwver_pkg is\n"
+c_BUILD_DAT   = "constant c_build_date : std_logic_vector(31 downto 0) := x\""
+c_SWITCH_HDL  = "constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x\""
+c_GENCORES    = "constant c_gencores_ver : std_logic_vector(31 downto 0) := x\""
+c_WRCORES     = "constant c_wrcores_ver : std_logic_vector(31 downto 0) := x\""
+c_PKG_TAIL    = "end package;\n";
+
+def main():
+  tl = subprocess.Popen("git rev-parse --show-toplevel", stdout=subprocess.PIPE, shell=True)
+  toplevel = tl.stdout.read()[0:-1] #remove trailing \n
+  f = open(toplevel+c_PKG_FILE, 'w')
+  f.write(c_PKG_LIB+c_PKG_HEAD)
+  #### DATE
+  day = datetime.datetime.today().day
+  mon = datetime.datetime.today().month
+  year = (datetime.datetime.today().year)%100
+  date = day<<24 | mon<<16 | year<<8
+  f.write(c_BUILD_DAT+hex(date)[2:].zfill(8)+"\";\n")
+  hash = subprocess.Popen("git log --pretty=format:'%h' -n 1", stdout=subprocess.PIPE, shell=True)
+  f.write(c_SWITCH_HDL+hash.stdout.read().zfill(8)+"\";\n")
+  hash = subprocess.Popen("(cd "+toplevel+"; git submodule status ip_cores/general-cores)", stdout=subprocess.PIPE, shell=True)
+  f.write(c_GENCORES+hash.stdout.read()[1:8].zfill(8)+"\";\n")
+  hash = subprocess.Popen("(cd "+toplevel+"; git submodule status ip_cores/wr-cores)", stdout=subprocess.PIPE, shell=True)
+  f.write(c_WRCORES+hash.stdout.read()[1:8].zfill(8)+"\";\n")
+  f.write(c_PKG_TAIL)
+  f.close()
+
+if __name__ == '__main__':
+    main()
--- a/modules/wrsw_hwiu/gw_ver_pkg.vhd
+++ b/modules/wrsw_hwiu/gw_ver_pkg.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+--generated automatically by gen_ver.py script--
+package hwver_pkg is
+constant c_build_date : std_logic_vector(31 downto 0) := x"05060d00";
+constant c_switch_hdl_ver : std_logic_vector(31 downto 0) := x"048d7667";
+constant c_gencores_ver : std_logic_vector(31 downto 0) := x"098938a2";
+constant c_wrcores_ver : std_logic_vector(31 downto 0) := x"0f2a6f97";
+end package;
--- a/modules/wrsw_hwiu/hwinfo_pkg.vhd
+++ b/modules/wrsw_hwiu/hwinfo_pkg.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wishbone_pkg.all;
+
+package hwinfo_pkg is
+
+  constant c_str_ver : integer := 1;
+  constant c_info_words  : integer := 4;
+
+  type t_words is array (natural range <>) of std_logic_vector(31 downto 0);
+
+  type t_hwinfo_struct is record
+    struct_ver  : std_logic_vector(7 downto 0);
+    nwords  : std_logic_vector(7 downto 0);
+    gw_ver  : std_logic_vector(15 downto 0);
+    w       : t_words(0 to c_info_words-1);
+  end record;
+
+  -- w(0) : date [Day(1B) Month(1B) Year(1B) Build(1B)]
+  -- w(1) : wr-switch-hdl hash
+  -- w(2) : general-cores hash
+  -- w(3) : wr-cores hash
+  
+  function f_pack_info_header (hw : t_hwinfo_struct) return std_logic_vector;
+
+  component xwrsw_hwiu
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+      g_address_granularity : t_wishbone_address_granularity := BYTE;
+      g_ndbg_regs           : integer                        := 1;
+      g_ver_major           : integer;
+      g_ver_minor           : integer;
+      g_build               : integer                        := 0);
+    port(
+      rst_n_i : in std_logic;
+      clk_i   : in std_logic;
+  
+      dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0) := (others=>'0');
+  
+      wb_i : in  t_wishbone_slave_in;
+      wb_o : out t_wishbone_slave_out);
+  end component;
+
+
+end package;
+
+package body hwinfo_pkg is
+
+  function f_pack_info_header (hw : t_hwinfo_struct) return std_logic_vector is
+    variable word : std_logic_vector(31 downto 0);
+  begin
+    word(31 downto 24) := hw.struct_ver;
+    word(23 downto 16) := hw.nwords;
+    word(15 downto 0)  := hw.gw_ver;
+    return word;
+  end function;
+
+end hwinfo_pkg;
--- a/modules/wrsw_hwiu/hwiu_wbgen2_pkg.vhd
+++ b/modules/wrsw_hwiu/hwiu_wbgen2_pkg.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Switch Hardware Info Unit
+---------------------------------------------------------------------------------------
+-- File           : hwiu_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from wrsw_hwiu.wb
+-- Created        : Mon Jun  3 17:21:40 2013
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_hwiu.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package hwiu_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_hwiu_in_registers is record
+    cr_rd_err_i                              : std_logic;
+    cr_rd_en_i                               : std_logic;
+    reg_val_i                                : std_logic_vector(31 downto 0);
+    end record;
+  
+  constant c_hwiu_in_registers_init_value: t_hwiu_in_registers := (
+    cr_rd_err_i => '0',
+    cr_rd_en_i => '0',
+    reg_val_i => (others => '0')
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_hwiu_out_registers is record
+      cr_adr_o                                 : std_logic_vector(15 downto 0);
+      cr_rd_en_o                               : std_logic;
+      cr_rd_en_load_o                          : std_logic;
+      end record;
+    
+    constant c_hwiu_out_registers_init_value: t_hwiu_out_registers := (
+      cr_adr_o => (others => '0'),
+      cr_rd_en_o => '0',
+      cr_rd_en_load_o => '0'
+      );
+    function "or" (left, right: t_hwiu_in_registers) return t_hwiu_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body hwiu_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if(x = 'X' or x = 'U') then
+return '0';
+else
+return x;
+end if; 
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_hwiu_in_registers) return t_hwiu_in_registers is
+variable tmp: t_hwiu_in_registers;
+begin
+tmp.cr_rd_err_i := f_x_to_zero(left.cr_rd_err_i) or f_x_to_zero(right.cr_rd_err_i);
+tmp.cr_rd_en_i := f_x_to_zero(left.cr_rd_en_i) or f_x_to_zero(right.cr_rd_en_i);
+tmp.reg_val_i := f_x_to_zero(left.reg_val_i) or f_x_to_zero(right.reg_val_i);
+return tmp;
+end function;
+end package body;
--- a/modules/wrsw_hwiu/hwiu_wishbone_slave.vhd
+++ b/modules/wrsw_hwiu/hwiu_wishbone_slave.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for WR Switch Hardware Info Unit
+---------------------------------------------------------------------------------------
+-- File           : hwiu_wishbone_slave.vhd
+-- Author         : auto-generated by wbgen2 from wrsw_hwiu.wb
+-- Created        : Mon Jun  3 17:21:40 2013
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_hwiu.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.hwiu_wbgen2_pkg.all;
+
+
+entity hwiu_wishbone_slave is
+  port (
+    rst_n_i                                  : in     std_logic;
+    clk_sys_i                                : in     std_logic;
+    wb_adr_i                                 : in     std_logic_vector(0 downto 0);
+    wb_dat_i                                 : in     std_logic_vector(31 downto 0);
+    wb_dat_o                                 : out    std_logic_vector(31 downto 0);
+    wb_cyc_i                                 : in     std_logic;
+    wb_sel_i                                 : in     std_logic_vector(3 downto 0);
+    wb_stb_i                                 : in     std_logic;
+    wb_we_i                                  : in     std_logic;
+    wb_ack_o                                 : out    std_logic;
+    wb_stall_o                               : out    std_logic;
+    regs_i                                   : in     t_hwiu_in_registers;
+    regs_o                                   : out    t_hwiu_out_registers
+  );
+end hwiu_wishbone_slave;
+
+architecture syn of hwiu_wishbone_slave is
+
+signal hwiu_cr_adr_int                          : std_logic_vector(15 downto 0);
+signal ack_sreg                                 : std_logic_vector(9 downto 0);
+signal rddata_reg                               : std_logic_vector(31 downto 0);
+signal wrdata_reg                               : std_logic_vector(31 downto 0);
+signal bwsel_reg                                : std_logic_vector(3 downto 0);
+signal rwaddr_reg                               : std_logic_vector(0 downto 0);
+signal ack_in_progress                          : std_logic      ;
+signal wr_int                                   : std_logic      ;
+signal rd_int                                   : std_logic      ;
+signal allones                                  : std_logic_vector(31 downto 0);
+signal allzeros                                 : std_logic_vector(31 downto 0);
+
+begin
+-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
+  wrdata_reg <= wb_dat_i;
+  bwsel_reg <= wb_sel_i;
+  rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
+  wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
+  allones <= (others => '1');
+  allzeros <= (others => '0');
+-- 
+-- Main register bank access process.
+  process (clk_sys_i, rst_n_i)
+  begin
+    if (rst_n_i = '0') then 
+      ack_sreg <= "0000000000";
+      ack_in_progress <= '0';
+      rddata_reg <= "00000000000000000000000000000000";
+      hwiu_cr_adr_int <= "0000000000000000";
+      regs_o.cr_rd_en_load_o <= '0';
+    elsif rising_edge(clk_sys_i) then
+-- advance the ACK generator shift register
+      ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
+      ack_sreg(9) <= '0';
+      if (ack_in_progress = '1') then
+        if (ack_sreg(0) = '1') then
+          regs_o.cr_rd_en_load_o <= '0';
+          ack_in_progress <= '0';
+        else
+          regs_o.cr_rd_en_load_o <= '0';
+        end if;
+      else
+        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
+          case rwaddr_reg(0) is
+          when '0' => 
+            if (wb_we_i = '1') then
+              hwiu_cr_adr_int <= wrdata_reg(15 downto 0);
+              regs_o.cr_rd_en_load_o <= '1';
+            end if;
+            rddata_reg(15 downto 0) <= hwiu_cr_adr_int;
+            rddata_reg(30) <= regs_i.cr_rd_err_i;
+            rddata_reg(31) <= regs_i.cr_rd_en_i;
+            rddata_reg(16) <= 'X';
+            rddata_reg(17) <= 'X';
+            rddata_reg(18) <= 'X';
+            rddata_reg(19) <= 'X';
+            rddata_reg(20) <= 'X';
+            rddata_reg(21) <= 'X';
+            rddata_reg(22) <= 'X';
+            rddata_reg(23) <= 'X';
+            rddata_reg(24) <= 'X';
+            rddata_reg(25) <= 'X';
+            rddata_reg(26) <= 'X';
+            rddata_reg(27) <= 'X';
+            rddata_reg(28) <= 'X';
+            rddata_reg(29) <= 'X';
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when '1' => 
+            if (wb_we_i = '1') then
+            end if;
+            rddata_reg(31 downto 0) <= regs_i.reg_val_i;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when others =>
+-- prevent the slave from hanging the bus on invalid address
+            ack_in_progress <= '1';
+            ack_sreg(0) <= '1';
+          end case;
+        end if;
+      end if;
+    end if;
+  end process;
+  
+  
+-- Drive the data output bus
+  wb_dat_o <= rddata_reg;
+-- Address of the register
+  regs_o.cr_adr_o <= hwiu_cr_adr_int;
+-- Read error
+-- Read register value
+  regs_o.cr_rd_en_o <= wrdata_reg(31);
+-- register value
+  rwaddr_reg <= wb_adr_i;
+  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
+-- ACK signal generation. Just pass the LSB of ACK counter.
+  wb_ack_o <= ack_sreg(0);
+end syn;
--- a/modules/wrsw_hwiu/wrsw_hwiu.vhd
+++ b/modules/wrsw_hwiu/wrsw_hwiu.vhd
+-------------------------------------------------------------------------------
+-- Title      : Hardware Info Unit
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : wrsw_hwiu.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Created    : 2013-03-26
+-- Last update: 2013-06-05
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- std-logic-based wrapper for xwrsw_hwiu module.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Grzegorz Daniluk / CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-03-26  0.1      greg.d          Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.wishbone_pkg.all;
+use work.hwinfo_pkg.all;
+
+entity wrsw_hwiu is
+  generic (
+    g_ndbg_regs : integer := 1;
+    g_ver_major : integer;
+    g_ver_minor : integer;
+    g_build     : integer := 0);
+  port(
+    rst_n_i : in std_logic;
+    clk_i   : in std_logic;
+
+    dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0) := (others => '0');
+
+    wb_adr_i   : in  std_logic_vector(0 downto 0);
+    wb_dat_i   : in  std_logic_vector(31 downto 0);
+    wb_dat_o   : out std_logic_vector(31 downto 0);
+    wb_cyc_i   : in  std_logic;
+    wb_sel_i   : in  std_logic_vector(3 downto 0);
+    wb_stb_i   : in  std_logic;
+    wb_we_i    : in  std_logic;
+    wb_ack_o   : out std_logic;
+    wb_stall_o : out std_logic;
+    wb_int_o   : out std_logic);
+end wrsw_hwiu;
+
+architecture behav of wrsw_hwiu is
+
+  component xwrsw_hwiu
+    generic (
+      g_interface_mode      : t_wishbone_interface_mode;
+      g_address_granularity : t_wishbone_address_granularity;
+      g_ndbg_regs           : integer;
+      g_ver_major           : integer;
+      g_ver_minor           : integer;
+      g_build               : integer);
+    port(
+      rst_n_i : in std_logic;
+      clk_i   : in std_logic;
+
+      dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0);
+
+      wb_i : in  t_wishbone_slave_in;
+      wb_o : out t_wishbone_slave_out);
+  end component;
+
+  signal wb_in  : t_wishbone_slave_in;
+  signal wb_out : t_wishbone_slave_out;
+
+begin
+
+  U_XHWIU : xwrsw_hwiu
+    generic map (
+      g_interface_mode      => PIPELINED,
+      g_address_granularity => WORD,
+      g_ndbg_regs           => g_ndbg_regs,
+      g_ver_major           => g_ver_major,
+      g_ver_minor           => g_ver_minor,
+      g_build               => g_build)
+    port map(
+      rst_n_i => rst_n_i,
+      clk_i   => clk_i,
+
+      dbg_regs_i => dbg_regs_i,
+
+      wb_i => wb_in,
+      wb_o => wb_out
+    );
+
+  wb_in.adr(0)           <= wb_adr_i(0);
+  wb_in.adr(31 downto 0) <= (others => '0');
+  wb_in.dat              <= wb_dat_i;
+  wb_in.cyc              <= wb_cyc_i;
+  wb_in.stb              <= wb_stb_i;
+  wb_in.sel              <= wb_sel_i;
+  wb_in.we               <= wb_we_i;
+  wb_dat_o               <= wb_out.dat;
+  wb_ack_o               <= wb_out.ack;
+  wb_stall_o             <= wb_out.stall;
+  wb_int_o               <= wb_out.int;
+
+end behav;
--- a/modules/wrsw_hwiu/wrsw_hwiu.wb
+++ b/modules/wrsw_hwiu/wrsw_hwiu.wb
+-- -*- Mode: LUA; tab-width: 2 -*-
+-- White-Rabbit Hardware Debugging Unit
+-- author: Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
+--
+-- Use wbgen2 to generate code, documentation and more.
+-- wbgen2 is available at:
+-- http://www.ohwr.org/projects/wishbone-gen
+--
+
+peripheral {
+ 
+  name = "WR Switch Hardware Info Unit";
+  description = "The module provides basic info about the gateware version. It can be also used for reading registers inside WR Switch Gateware after connecting them to optional dbg input.";
+  hdl_entity = "hwiu_wishbone_slave";
+  prefix = "hwiu";
+
+
+  reg {
+    name = "Control Register";
+    prefix = "CR";
+
+    field {
+        name = "Address of the register";
+        description = "Which register (among those connected to HWDU) will be read";
+        prefix = "ADR";
+        size = 16;
+        type = SLV;
+        access_bus = READ_WRITE;
+        access_dev = READ_ONLY;
+    };
+
+    field {
+        name = "Read error";
+        description = "read 1: read error, provided address is out of range \
+                       read 0: read done successfully";
+        prefix = "RD_ERR";
+        type = BIT;
+        align = 30;
+        access_bus = READ_ONLY;
+        access_dev = WRITE_ONLY;
+    };
+
+    field {
+       name = "Read register value";
+       description = "write 1: read the content \
+                      write 0: no effect \
+                      read  1: reading in progress \
+                      read  0: reading done, register value available";
+       prefix = "RD_EN";
+       
+       type = BIT;
+       align = 31;
+       access_dev = READ_WRITE;
+       access_bus = READ_WRITE;
+       load = LOAD_EXT;
+    };
+  };
+
+  reg {
+    name = "Value of the requested register";
+    description = "The value of the register under ADR from the Control Register";
+    prefix = "REG_VAL";
+
+    field {
+      name = "register value";
+      size = 32;
+      type = SLV;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+  };
+
+};
--- a/modules/wrsw_hwiu/xwrsw_hwiu.vhd
+++ b/modules/wrsw_hwiu/xwrsw_hwiu.vhd
+-------------------------------------------------------------------------------
+-- Title      : Hardware Info Unit wrapper
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : xwrsw_hwiu.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN BE-CO-HT
+-- Created    : 2013-03-26
+-- Last update: 2013-06-05
+-- Platform   : FPGA-generic
+-- Standard   : VHDL
+-------------------------------------------------------------------------------
+-- Description:
+-- Debugging module, allows reading the content of selected registers inside 
+-- WR Switch GW through Wishbone interface.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2013 Grzegorz Daniluk / CERN
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author          Description
+-- 2013-03-26  0.1      greg.d          Created
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.wishbone_pkg.all;
+use work.hwiu_wbgen2_pkg.all;
+use work.hwinfo_pkg.all;
+use work.hwver_pkg.all;
+
+entity xwrsw_hwiu is
+  generic (
+    g_interface_mode      : t_wishbone_interface_mode      := PIPELINED;
+    g_address_granularity : t_wishbone_address_granularity := BYTE;
+    g_ndbg_regs           : integer                        := 1;
+    g_ver_major           : integer;
+    g_ver_minor           : integer;
+    g_build               : integer                        := 0);
+  port(
+    rst_n_i : in std_logic;
+    clk_i   : in std_logic;
+
+    dbg_regs_i : in std_logic_vector(g_ndbg_regs*32-1 downto 0) := (others => '0');
+
+    wb_i : in  t_wishbone_slave_in;
+    wb_o : out t_wishbone_slave_out);
+end xwrsw_hwiu;
+
+architecture behav of xwrsw_hwiu is
+
+  component hwiu_wishbone_slave
+    port (
+      rst_n_i    : in  std_logic;
+      clk_sys_i  : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(0 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      regs_i     : in  t_hwiu_in_registers;
+      regs_o     : out t_hwiu_out_registers
+    );
+  end component;
+
+  signal wb_in  : t_wishbone_slave_in;
+  signal wb_out : t_wishbone_slave_out;
+
+  signal wb_regs_in  : t_hwiu_in_registers;
+  signal wb_regs_out : t_hwiu_out_registers;
+
+  type   t_rd_st is (IDLE, READ);
+  signal rd_state : t_rd_st;
+
+  signal rd_val        : std_logic_vector(31 downto 0);
+  signal rd_err, rd_en : std_logic;
+
+  constant c_dat_wrds : integer := c_info_words+1 +  -- HW Info
+                                   g_ndbg_regs;      -- Debug registers
+  --signal data : std_logic_vector( c_dat_wrds*32-1 downto 0);
+  signal data : t_words(0 to c_info_words+g_ndbg_regs);
+
+  -- regs for storing HW version info
+  signal hwinfo : t_hwinfo_struct;
+
+begin
+
+  U_Adapter : wb_slave_adapter
+    generic map (
+      g_master_use_struct  => true,
+      g_master_mode        => CLASSIC,
+      g_master_granularity => WORD,
+      g_slave_use_struct   => true,
+      g_slave_mode         => g_interface_mode,
+      g_slave_granularity  => g_address_granularity)
+    port map (
+      clk_sys_i => clk_i,
+      rst_n_i   => rst_n_i,
+      slave_i   => wb_i,
+      slave_o   => wb_o,
+      master_i  => wb_out,
+      master_o  => wb_in);
+
+  wb_out.err <= '0';
+  wb_out.rty <= '0';
+  wb_out.int <= '0';
+
+  U_WB_Slave : hwiu_wishbone_slave
+    port map(
+      rst_n_i    => rst_n_i,
+      clk_sys_i  => clk_i,
+      wb_adr_i   => wb_in.adr(0 downto 0),
+      wb_dat_i   => wb_in.dat,
+      wb_dat_o   => wb_out.dat,
+      wb_cyc_i   => wb_in.cyc,
+      wb_sel_i   => wb_in.sel,
+      wb_stb_i   => wb_in.stb,
+      wb_we_i    => wb_in.we,
+      wb_ack_o   => wb_out.ack,
+      wb_stall_o => wb_out.stall,
+      regs_i     => wb_regs_in,
+      regs_o     => wb_regs_out
+    );
+
+  -- fill HW Info regs
+  hwinfo.struct_ver          <= std_logic_vector(to_unsigned(c_str_ver, 8));
+  hwinfo.nwords              <= std_logic_vector(to_unsigned(c_info_words, 8));
+  hwinfo.gw_ver(15 downto 8) <= std_logic_vector(to_unsigned(g_ver_major, 8));
+  hwinfo.gw_ver(7 downto 0)  <= std_logic_vector(to_unsigned(g_ver_minor, 8));
+
+  hwinfo.w(0) <= c_build_date(31 downto 8) & std_logic_vector(to_unsigned(g_build, 8));
+  hwinfo.w(1) <= c_switch_hdl_ver;
+  hwinfo.w(2) <= c_gencores_ver;
+  hwinfo.w(3) <= c_wrcores_ver;
+
+  -- fill data available through HW info
+  data(0) <= f_pack_info_header(hwinfo);
+  GEN_HWINFO : for i in 0 to c_info_words-1 generate
+    data(i+1) <= hwinfo.w(i);
+  end generate;
+
+  GEN_DBGREGS : for i in 0 to g_ndbg_regs-1 generate
+    data(i+c_info_words+1) <= dbg_regs_i((i+1)*32-1 downto i*32);
+  end generate;
+
+  wb_regs_in.reg_val_i   <= rd_val;
+  wb_regs_in.cr_rd_err_i <= rd_err;
+  wb_regs_in.cr_rd_en_i  <= rd_en;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if(rst_n_i = '0') then
+        rd_state <= IDLE;
+        rd_en    <= '0';
+        rd_err   <= '0';
+      else
+        case(rd_state) is
+          when IDLE =>
+            if(wb_regs_out.cr_rd_en_o = '1' and wb_regs_out.cr_rd_en_load_o = '1') then
+              rd_en    <= '1';
+              rd_state <= READ;
+            end if;
+          when READ =>
+            rd_en    <= '0';
+            rd_state <= IDLE;
+            if(to_integer(unsigned(wb_regs_out.cr_adr_o)) > c_dat_wrds-1) then
+              rd_err <= '1';
+            else
+              rd_err <= '0';
+              --get part of dbg_regs input vector
+              rd_val <= data(to_integer(unsigned(wb_regs_out.cr_adr_o)));
+            end if;
+
+          when others =>
+            rd_state <= IDLE;
+        end case;
+      end if;
+    end if;
+  end process;
+
+end behav;