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White Rabbit Switch - Gateware
Commit 397bcc34 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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crude testbench

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testbench/include/axi4_lite_master.sv 0 → 100644
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`include "simdrv_defs.svh"
`include "if_wishbone_types.svh"
`include "if_wishbone_accessor.svh"
//`define USE_VHDL_BINDINGS 1
// for VHDL instances
`ifdef USE_VHDL_BINDINGS
import axi4_pkg::*;
`endif
interface IAXI4LiteMaster
(
input clk_i,
input rst_n_i
);
parameter g_addr_width = 32;
parameter g_data_width = 32;
logic arvalid;
logic awvalid;
logic bready;
logic rready;
logic wlast ;
logic wvalid;
logic [g_addr_width-1:0] araddr;
logic [g_addr_width-1:0] awaddr;
logic [g_data_width-1:0] wdata;
logic [g_data_width/8-1:0] wstrb;
logic arready;
logic awready;
logic bvalid;
logic rlast;
logic rvalid;
logic wready;
logic [1:0] bresp;
logic [1:0] rresp;
logic [g_data_width-1:0] rdata;
wire clk;
wire rst_n;
time last_access_t = 0;
modport master
(
output arvalid,
output awvalid,
output bready,
output rready,
output wlast ,
output wvalid,
output araddr,
output awaddr,
output wdata,
output wstrb,
input arready,
input awready,
input bvalid,
input rlast,
input rvalid,
input wready,
input bresp,
input rresp,
input rdata
);
`ifdef USE_VHDL_BINDINGS
t_axi4_lite_slave_in_32 master_out;
t_axi4_lite_slave_out_32 master_in;
modport vhdl
(
output master_out,
input master_in
);
assign master_out.arvalid = arvalid;
assign master_out.awvalid = awvalid;
assign master_out.bready = bready;
assign master_out.rready =rready;
assign master_out.wlast =wlast;
assign master_out.wvalid=wvalid;
assign master_out.araddr=araddr;
assign master_out.awaddr=awaddr;
assign master_out.wdata=wdata;
assign master_out.wstrb=wstrb;
assign arready=master_in.arready;
assign awready=master_in.awready;
assign bvalid=master_in.bvalid;
assign rlast=master_in.rlast;
assign rvalid=master_in.rvalid;
assign wready=master_in.wready;
assign bresp=master_in.bresp;
assign rresp=master_in.rresp;
assign rdata=master_in.rdata;
`endif
task automatic write_cycle
(
wb_xfer_t xfer,
ref wb_cycle_result_t result
);
if($time != last_access_t)
@(posedge clk_i); /* resynchronize, just in case */
// $display("AXI write addr %x data %x", xfer.a, xfer.d);
bready <= 0;
awvalid <= 1;
awaddr <= xfer.a;
@(posedge clk_i);
while(!awready)
@(posedge clk_i);
awvalid <= 0;
wdata <= xfer.d;
wstrb <= 'hf; // fixme
wlast <= 1;
wvalid <= 1;
while(!wready)
@(posedge clk_i);
wvalid <= 0;
while(!bvalid)
@(posedge clk_i);
bready <= 1;
@(posedge clk_i);
bready <= 0;
// $display("AXI response: %x", bresp);
result = R_OK;
last_access_t = $time;
endtask // automatic
task automatic read_cycle
(
ref wb_xfer_t xfer,
ref wb_cycle_result_t result
);
if($time != last_access_t)
@(posedge clk_i); /* resynchronize, just in case */
// $display("AXI read addr %x", xfer.a );
bready <= 0;
arvalid <= 1;
araddr <= xfer.a;
rready <= 0;
@(posedge clk_i);
while(!arready)
@(posedge clk_i);
arvalid <= 0;
while(!rvalid)
@(posedge clk_i);
rready <= 1;
// $display("AXI response: %x data %x", rresp, rdata);
xfer.d = rdata;
@(posedge clk_i);
rready <= 0;
result = R_OK;
last_access_t = $time;
endtask // automatic
reg xf_idle = 1;
wb_cycle_t request_queue[$];
wb_cycle_t result_queue[$];
class CAXI4LiteMasterAccessor extends CWishboneAccessor;
function automatic int poll();
return 0;
endfunction
task get(ref wb_cycle_t xfer);
while(!result_queue.size())
@(posedge clk_i);
xfer = result_queue.pop_front();
endtask
task clear();
endtask // clear
task put(ref wb_cycle_t xfer);
// $display("WBMaster[%d]: PutCycle",g_data_width);
request_queue.push_back(xfer);
endtask // put
function int idle();
return (request_queue.size() == 0) && xf_idle;
endfunction // idle
endclass // CIWBMasterAccessor
function CAXI4LiteMasterAccessor get_accessor();
CAXI4LiteMasterAccessor tmp;
tmp = new;
return tmp;
endfunction // get_accessoror
always@(posedge clk_i)
if(!rst_n_i)
begin
request_queue = {};
result_queue = {};
arvalid = 0;
awvalid = 0;
wvalid = 0;
bready = 0;
rready = 0;
end
initial forever
begin
@(posedge clk_i);
if(request_queue.size() > 0)
begin
wb_cycle_t c;
wb_cycle_result_t res;
c = request_queue.pop_front();
if(c.rw)
write_cycle(c.data[0], res);
else
read_cycle(c.data[0], res);
c.result =res;
result_queue.push_back(c);
end
end
endinterface
`define WIRE_AXI4_FULL_PINS(pin_prefix,signal_prefix_in,signal_prefix_out)\
.``pin_prefix``awid(``signal_prefix_in``awid),\
.``pin_prefix``awaddr(``signal_prefix_in``awaddr),\
.``pin_prefix``awlen(``signal_prefix_in``awlen),\
.``pin_prefix``awsize(``signal_prefix_in``awsize),\
.``pin_prefix``awburst(``signal_prefix_in``awburst),\
.``pin_prefix``awlock(``signal_prefix_in``awlock),\
.``pin_prefix``awcache(``signal_prefix_in``awcache),\
.``pin_prefix``awprot(``signal_prefix_in``awprot),\
.``pin_prefix``awqos(``signal_prefix_in``awqos),\
.``pin_prefix``awvalid(``signal_prefix_in``awvalid),\
.``pin_prefix``awready(``signal_prefix_out``awready),\
.``pin_prefix``wdata(``signal_prefix_in``wdata),\
.``pin_prefix``wstrb(``signal_prefix_in``wstrb),\
.``pin_prefix``wlast(``signal_prefix_in``wlast),\
.``pin_prefix``wvalid(``signal_prefix_in``wvalid),\
.``pin_prefix``wready(``signal_prefix_out``wready),\
.``pin_prefix``bready(``signal_prefix_in``bready),\
.``pin_prefix``bid(``signal_prefix_out``bid),\
.``pin_prefix``bresp(``signal_prefix_out``bresp),\
.``pin_prefix``bvalid(``signal_prefix_out``bvalid),\
.``pin_prefix``arid(``signal_prefix_in``arid),\
.``pin_prefix``araddr(``signal_prefix_in``araddr),\
.``pin_prefix``arlen(``signal_prefix_in``arlen),\
.``pin_prefix``arsize(``signal_prefix_in``arsize),\
.``pin_prefix``arburst(``signal_prefix_in``arburst),\
.``pin_prefix``arlock(``signal_prefix_in``arlock),\
.``pin_prefix``arcache(``signal_prefix_in``arcache),\
.``pin_prefix``arprot(``signal_prefix_in``arprot),\
.``pin_prefix``arqos(``signal_prefix_in``arqos),\
.``pin_prefix``arvalid(``signal_prefix_in``arvalid),\
.``pin_prefix``arready(``signal_prefix_out``arready),\
.``pin_prefix``rready(``signal_prefix_in``rready),\
.``pin_prefix``rid(``signal_prefix_out``rid),\
.``pin_prefix``rdata(``signal_prefix_out``rdata),\
.``pin_prefix``rresp(``signal_prefix_out``rresp),\
.``pin_prefix``rlast(``signal_prefix_out``rlast),\
.``pin_prefix``rvalid(``signal_prefix_out``rvalid)
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